From 62789094bb4079a024be518ecbe79efa68f62d9d Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Wed, 25 Mar 2015 01:02:22 -0400 Subject: streamline(?) api_mux, register data for eim output --- src/rtl/trng_csprng.v | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src/rtl/trng_csprng.v') diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v index f985be4..0797208 100644 --- a/src/rtl/trng_csprng.v +++ b/src/rtl/trng_csprng.v @@ -160,6 +160,7 @@ module trng_csprng( // Wires. //---------------------------------------------------------------- reg [31 : 0] tmp_read_data; + reg [31 : 0] tmp_read_data_reg; reg tmp_error; reg cipher_init; @@ -184,7 +185,7 @@ module trng_csprng( //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- - assign read_data = tmp_read_data; + assign read_data = tmp_read_data_reg; assign error = tmp_error; assign seed_ack = seed_ack_reg; assign more_seed = more_seed_reg; @@ -430,6 +431,12 @@ module trng_csprng( end end // cspng_api_logic + // register data for eim output + always @(posedge clk) + begin + tmp_read_data_reg <= tmp_read_data; + end + //---------------------------------------------------------------- // block_ctr -- cgit v1.2.3