From c1d4e1c8840f10cc24381a29437a8ed71b101bd2 Mon Sep 17 00:00:00 2001
From: Paul Selkirk <paul@psgd.org>
Date: Tue, 17 Nov 2015 23:42:34 -0500
Subject: Harmonize status valid bit with other cores.

---
 src/rtl/trng_csprng.v | 4 ++--
 src/rtl/trng_mixer.v  | 1 -
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v
index c0a0c12..0f886d2 100644
--- a/src/rtl/trng_csprng.v
+++ b/src/rtl/trng_csprng.v
@@ -74,7 +74,7 @@ module trng_csprng(
   localparam CTRL_SEED_BIT         = 1;
 
   localparam ADDR_STATUS           = 8'h09;
-  localparam STATUS_RND_VALID_BIT  = 0;
+  localparam STATUS_RND_VALID_BIT  = 1;
 
   localparam ADDR_STAT_BLOCKS_LOW  = 8'h14;
   localparam ADDR_STAT_BLOCKS_HIGH = 8'h15;
@@ -428,7 +428,7 @@ module trng_csprng(
                     tmp_read_data = {30'h00000000, seed_reg, enable_reg};
 
                 ADDR_STATUS:
-                    tmp_read_data = {30'h00000000, ready_reg, rnd_syn};
+                    tmp_read_data = {30'h00000000, rnd_syn, ready_reg};
 
                 ADDR_STAT_BLOCKS_LOW:
                   tmp_read_data = block_stat_ctr_reg[31 : 0];
diff --git a/src/rtl/trng_mixer.v b/src/rtl/trng_mixer.v
index 32d9216..9ee0094 100644
--- a/src/rtl/trng_mixer.v
+++ b/src/rtl/trng_mixer.v
@@ -494,7 +494,6 @@ module trng_mixer(
     begin : mixer_api_logic
       enable_new          = 0;
       enable_we           = 0;
-      restart_reg         = 0;
       restart_new         = 0;
       entropy_timeout_new = 24'h000000;
       entropy_timeout_we  = 0;
-- 
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