From 7578afe1a28e932a2b6ae3493348d0c347e9b682 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 17 Jul 2015 17:31:57 +0200 Subject: Adding more test functionality in the fifo testbench. Now we generates several 512-bit words fed into the fifo. --- src/tb/tb_csprng_fifo.v | 115 +++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 104 insertions(+), 11 deletions(-) diff --git a/src/tb/tb_csprng_fifo.v b/src/tb/tb_csprng_fifo.v index 91044a5..8b01ce0 100644 --- a/src/tb/tb_csprng_fifo.v +++ b/src/tb/tb_csprng_fifo.v @@ -143,9 +143,19 @@ module tb_csprng_fifo(); $display("cycle: 0x%016x", cycle_ctr); $display("State of DUT"); $display("------------"); + $display("inputs:"); + $display("more_data = 0x%01x, data_valid = 0x%01x", + tb_more_data, tb_csprng_data_valid); + $display("input_data = 0x%0128x", tb_csprng_data); + $display(""); + $display("outputs:"); $display("rnd_syn = 0x%01x, rnd_ack = 0x%01x, rnd_data = 0x%08x", tb_rnd_syn, tb_rnd_ack, tb_rnd_data); $display(""); + $display("internals:"); + $display("rd_ptr = 0x%02x, wr_ptr = 0x%02x, fifo_ctr = 0x%02x, mux_ptr = 0x%02x", + dut.rd_ptr_reg, dut.wr_ptr_reg, dut.fifo_ctr_reg, dut.mux_data_ptr_reg); + $display(""); end endtask // dump_dut_state @@ -156,15 +166,15 @@ module tb_csprng_fifo(); // Generate test data with distinct patterns as requested // by the dut. //---------------------------------------------------------------- - always @ (posedge tb_more_data) - begin - for (i = 0 ; i < 16 ; i = i + 1) - tb_csprng_data[i * 32 +: 32] = tb_csprng_data[i * 32 +: 32] + 32'h10101010; - - tb_csprng_data_valid = 1'b1; - #(2 * CLK_PERIOD); - tb_csprng_data_valid = 1'b0; - end +// always @ (posedge tb_more_data) +// begin +// for (i = 0 ; i < 16 ; i = i + 1) +// tb_csprng_data[i * 32 +: 32] = tb_csprng_data[i * 32 +: 32] + 32'h10101010; +// +// tb_csprng_data_valid = 1'b1; +// #(2 * CLK_PERIOD); +// tb_csprng_data_valid = 1'b0; +// end //---------------------------------------------------------------- @@ -225,10 +235,89 @@ module tb_csprng_fifo(); tb_write_data = 32'h00000000; tb_discard = 0; - tb_rnd_ack = 1; + tb_rnd_ack = 0; for (i = 0 ; i < 16 ; i = i + 1) - tb_csprng_data[i * 32 +: 32] = {i, i, i, i}; + tb_csprng_data[i * 32 +: 32] = 32'h0; + tb_csprng_data_valid = 0; + + end + endtask // init_sim + + + //---------------------------------------------------------------- + // write_w512() + // + // Writes a 512 bit data word into the fifo. + //---------------------------------------------------------------- + task write_w512(input [511 : 0] w512); + begin + tb_csprng_data = w512; + tb_csprng_data_valid = 1; + #(CLK_PERIOD); + tb_csprng_data_valid = 0; + end + endtask // write_w512 + + + //---------------------------------------------------------------- + // fifo_test() + // + // Writes a number of 512-bit words to the FIFO and then + // extracts 32-bit words and checks that we get the correct + // words all the time. + //---------------------------------------------------------------- + task fifo_test(); + reg [7 : 0] i; + reg [7 : 0] j; + reg [511 : 0] w512; + reg [31 : 0] w00; + reg [31 : 0] w01; + reg [31 : 0] w02; + reg [31 : 0] w03; + reg [31 : 0] w04; + reg [31 : 0] w05; + reg [31 : 0] w06; + reg [31 : 0] w07; + reg [31 : 0] w08; + reg [31 : 0] w09; + reg [31 : 0] w10; + reg [31 : 0] w11; + reg [31 : 0] w12; + reg [31 : 0] w13; + reg [31 : 0] w14; + reg [31 : 0] w15; + + begin + i = 8'd0; + + // Filling up the memory with data. + for (j = 0 ; j < 4 ; j = j + 1) + begin + w00 = {(i + 8'd15), (i + 8'd15), (i + 8'd15), (i + 8'd15)}; + w01 = {(i + 8'd14), (i + 8'd14), (i + 8'd14), (i + 8'd14)}; + w02 = {(i + 8'd13), (i + 8'd13), (i + 8'd13), (i + 8'd13)}; + w03 = {(i + 8'd12), (i + 8'd12), (i + 8'd12), (i + 8'd12)}; + w04 = {(i + 8'd11), (i + 8'd11), (i + 8'd11), (i + 8'd11)}; + w05 = {(i + 8'd10), (i + 8'd10), (i + 8'd10), (i + 8'd10)}; + w06 = {(i + 8'd09), (i + 8'd09), (i + 8'd09), (i + 8'd09)}; + w07 = {(i + 8'd08), (i + 8'd08), (i + 8'd08), (i + 8'd08)}; + + w08 = {(i + 8'd07), (i + 8'd07), (i + 8'd07), (i + 8'd07)}; + w09 = {(i + 8'd06), (i + 8'd06), (i + 8'd06), (i + 8'd06)}; + w10 = {(i + 8'd05), (i + 8'd05), (i + 8'd05), (i + 8'd05)}; + w11 = {(i + 8'd04), (i + 8'd04), (i + 8'd04), (i + 8'd04)}; + w12 = {(i + 8'd03), (i + 8'd03), (i + 8'd03), (i + 8'd03)}; + w13 = {(i + 8'd02), (i + 8'd02), (i + 8'd02), (i + 8'd02)}; + w14 = {(i + 8'd01), (i + 8'd01), (i + 8'd01), (i + 8'd01)}; + w15 = {(i + 8'd00), (i + 8'd00), (i + 8'd00), (i + 8'd00)}; + + w512 = {w00, w01, w02, w03, w04, w05, w06, w07, + w08, w09, w10, w11, w12, w13, w14, w15}; + + write_w512(w512); + i = i + 16; + end end endtask // init_sim @@ -252,6 +341,10 @@ module tb_csprng_fifo(); #(100 * CLK_PERIOD) + fifo_test(); + + #(100 * CLK_PERIOD) + display_test_results(); $display(""); -- cgit v1.2.3