core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Collapse)	Author
2015-08-27	Removed the temporary task for generating seeds that is obsoleted by the ↵	Joachim Strömbergson
	seed process.
2015-08-27	Added process to generate need seeds with differentg patterns and ↵	Joachim Strömbergson
	communicate with the DUT using the seed update protocol. Minor nits.
2015-08-26	(1) Removed obsolete dump of values from the monitor. (2) Changed to using ↵	Joachim Strömbergson
	proper API write_word.
2015-08-26	Adding test case for verifying reseed functionality in csprng.	Joachim Strömbergson

2015-08-20	Adding a stat counter for number of CSPRNG reseeds.	Joachim Strömbergson

2015-07-18	Read out all data in the fifo by looking at the syn flag. The fifo simulates ok.	Joachim Strömbergson

2015-07-18	Fixed replication sizes found during lintint.	Joachim Strömbergson

2015-07-18	Writing a new word into the fifo.	Joachim Strömbergson

2015-07-18	Adding task for reading words from the fifo. Reading out more than 16 words. ↵	Joachim Strömbergson
	Refactored w512 task.
2015-07-18	Simplified the pointer handling. Fixed size of counter. Now all positions in ↵	Joachim Strömbergson
	the fifo is used and flags are correctly set.
2015-07-17	Adding more functionality to observe the fifo during test.	Joachim Strömbergson

2015-07-17	Adding task to dump fifo contents.	Joachim Strömbergson

2015-07-17	Adding more test functionality in the fifo testbench. Now we generates ↵	Joachim Strömbergson
	several 512-bit words fed into the fifo.
2015-05-22	(1) Added a cipher block statistics counter. (2) Cleaned up the csprng code ↵	Joachim Strömbergson
	and connected discard for fast restart of trng. (3) Added addresses for allowing API to write a known seed to allow test mode. (3) Fixed a number of minor issues during linting. (4) Fixed the csprng testbench to actually generate data as well as displaying the block stat counter.
2015-04-28	(1) Remove the delayed read for EIM (see core/platform/novena commit ↵	Paul Selkirk
	2f58e8f). (2) Add the code to read the csprng name and version registers.
2015-04-27	Adding name and version fields to the csprng.	Joachim Strömbergson

2015-04-27	Updated the trng version number to sometning that better reflects that it ↵	Joachim Strömbergson
	actually builds and generates values.
2015-04-02	(1) Added a state in the write fifo machine to actually drop request between ↵	Joachim Strömbergson
	csprng data words. (2) Updated the testbench with better test vector generation.
2015-04-02	Fixed syntax and added init functionality for testing the dut.	Joachim Strömbergson

2015-04-01	Adding initial version of testbench for the csprng fifo.	Joachim Strömbergson

2015-04-01	Adding fake entropy providers to allow us to simulate the complete trng.	Joachim Strömbergson

2015-04-01	Cleanup and fixes of calculations.	Joachim Strömbergson

2015-03-26	Minor cleanup: Morged clocked processes. Changed name of api read data hold ↵	Joachim Strömbergson
	register. Changed to localparam. Removed redundant code for reg updates.
2015-03-26	Minor cleanup: Changed to localparam for internal parameters. Merged reg ↵	Joachim Strömbergson
	update processes to one. Changed name of api read data hold reg and added better update vector name for it.
2015-03-26	Changed to Verilog 2001 part select for word extraction.	Joachim Strömbergson

2015-03-26	More cleanup. Completed parameterization of fifo. Fixed incorrect size of ↵	Joachim Strömbergson
	control regs.
2015-03-26	Cleanup from linting. Changing to parameterized fifo pointers. Fixed bug in ↵	Joachim Strömbergson
	bit selection.
2015-03-26	Cleanup: Merged separate clocked processes. Fixed incorrect bit widths. ↵	Joachim Strömbergson
	Changed to localparams. Changed api data read reg to real hold register.
2015-03-25	streamline(?) api_mux, register data for eim output	Paul Selkirk

2014-11-20	Updates of variable names to matched changed instance name and new fifo.	Joachim Strömbergson

2014-11-20	Reworked the csprng output fifo to really take advantage of the fact that ↵	Joachim Strömbergson
	the csprng delivers blocks of 512 bits. Removed trailing whitespaces and linted code.
2014-11-20	Updates after linting.	Joachim Strömbergson

2014-11-20	(1) Reducing timepout for entropy sources. Updated interface for sha-512 to ↵	Joachim Strömbergson
	match new interface with work factor ports. We are not using the work factor here at the moment.
2014-10-02	Updating testbenches to match new interfaces and use the api to read and ↵	Joachim Strömbergson
	write data.
2014-10-02	Removing wrappers since they are not used.	Joachim Strömbergson

2014-10-02	Updating trng to debugged version.	Joachim Strömbergson

2014-09-27	Adding debug port for mixer and csprng. In the csprng the debug_update will ↵	Joachim Strömbergson
	trigger fifo extraction and thus force random number generation.
2014-09-26	Updating source to the latest and greatest. In this version the entropy ↵	Joachim Strömbergson
	sources works and all modules have correct intterface.
2014-09-26	Removing old fake entropy source.	Joachim Strömbergson

2014-09-26	Removing old fake module for ring oscillator.	Joachim Strömbergson

2014-09-18	Updates after synthesis of the complete trng.	Joachim Strömbergson

2014-09-16	Adding a minor readme to explain when to use the entropy wrappers.	Joachim Strömbergson

2014-09-16	Adding initial version of wrapper for the avalance entropy core to be used ↵	Joachim Strömbergson
	during synthesis.
2014-09-16	Fixed incorrect bit index.	Joachim Strömbergson

2014-09-16	More debug fixes. We add one extra wait cycle to allow the mixer to detect ↵	Joachim Strömbergson
	that we want more seed.
2014-09-16	Debug fixes found during simulation. Now the trng generates data and ↵	Joachim Strömbergson
	provides an api.
2014-09-12	Adding first version of complete trng.	Joachim Strömbergson

2014-09-12	Adding testbench for the complete trng.	Joachim Strömbergson

2014-09-12	Adding fake modules for the three types of entropy sources to allow us to ↵	Joachim Strömbergson
	simulate with known values.
2014-09-11	Update after completion of rtl and debug of rtl using the updated testbench. ↵	Joachim Strömbergson
	Now it works.