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True Random Number Generator core implemented in Verilog
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2014-09-26
Removing old fake entropy source.
Joachim Strömbergson
2014-09-26
Removing old fake module for ring oscillator.
Joachim Strömbergson
2014-09-18
Updates after synthesis of the complete trng.
Joachim Strömbergson
2014-09-16
Adding a minor readme to explain when to use the entropy wrappers.
Joachim Strömbergson
2014-09-16
Adding initial version of wrapper for the avalance entropy core to be used du...
Joachim Strömbergson
2014-09-16
Fixed incorrect bit index.
Joachim Strömbergson
2014-09-16
More debug fixes. We add one extra wait cycle to allow the mixer to detect th...
Joachim Strömbergson
2014-09-16
Debug fixes found during simulation. Now the trng generates data and provides...
Joachim Strömbergson
2014-09-12
Adding first version of complete trng.
Joachim Strömbergson
2014-09-12
Adding testbench for the complete trng.
Joachim Strömbergson
2014-09-12
Adding fake modules for the three types of entropy sources to allow us to sim...
Joachim Strömbergson
2014-09-11
Update after completion of rtl and debug of rtl using the updated testbench. ...
Joachim Strömbergson
2014-09-11
Adding initial versions of rtl and tb for the mixer.
Joachim Strömbergson
2014-09-11
Adding rtl and tb for the csprng part of the trng.
Joachim Strömbergson