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True Random Number Generator core implemented in Verilog
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2015-07-18
Adding task for reading words from the fifo. Reading out more than 16 words. ...
Joachim Strömbergson
2015-07-17
Adding more functionality to observe the fifo during test.
Joachim Strömbergson
2015-07-17
Adding task to dump fifo contents.
Joachim Strömbergson
2015-07-17
Adding more test functionality in the fifo testbench. Now we generates severa...
Joachim Strömbergson
2015-05-22
(1) Added a cipher block statistics counter. (2) Cleaned up the csprng code a...
Joachim Strömbergson
2015-04-02
(1) Added a state in the write fifo machine to actually drop request between ...
Joachim Strömbergson
2015-04-02
Fixed syntax and added init functionality for testing the dut.
Joachim Strömbergson
2015-04-01
Adding initial version of testbench for the csprng fifo.
Joachim Strömbergson
2015-04-01
Adding fake entropy providers to allow us to simulate the complete trng.
Joachim Strömbergson
2014-11-20
Updates of variable names to matched changed instance name and new fifo.
Joachim Strömbergson
2014-10-02
Updating testbenches to match new interfaces and use the api to read and writ...
Joachim Strömbergson
2014-09-26
Removing old fake entropy source.
Joachim Strömbergson
2014-09-26
Removing old fake module for ring oscillator.
Joachim Strömbergson
2014-09-12
Adding testbench for the complete trng.
Joachim Strömbergson
2014-09-12
Adding fake modules for the three types of entropy sources to allow us to sim...
Joachim Strömbergson
2014-09-11
Update after completion of rtl and debug of rtl using the updated testbench. ...
Joachim Strömbergson
2014-09-11
Adding initial versions of rtl and tb for the mixer.
Joachim Strömbergson
2014-09-11
Adding rtl and tb for the csprng part of the trng.
Joachim Strömbergson