| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-10-16 | (1) Fixed width definitions and cleaned up constants as part of checking ↵HEADmaster | Joachim Strömbergson | |
| that all registers are being reset. (2) Cleaned up tasks and removed timescale directives to silence lint. | |||
| 2014-10-02 | Updating testbenches to match new interfaces and use the api to read and ↵ | Joachim Strömbergson | |
| write data. | |||
| 2014-09-12 | Adding testbench for the complete trng. | Joachim Strömbergson | |
 |
index : core/rng/trng | |
| True Random Number Generator core implemented in Verilog | git repositories |
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