core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Collapse)	Author
2015-07-17	Adding task to dump fifo contents.	Joachim Strömbergson

2015-07-17	Adding more test functionality in the fifo testbench. Now we generates ↵	Joachim Strömbergson
	several 512-bit words fed into the fifo.
2015-04-02	(1) Added a state in the write fifo machine to actually drop request between ↵	Joachim Strömbergson
	csprng data words. (2) Updated the testbench with better test vector generation.
2015-04-02	Fixed syntax and added init functionality for testing the dut.	Joachim Strömbergson

2015-04-01	Adding initial version of testbench for the csprng fifo.	Joachim Strömbergson