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True Random Number Generator core implemented in Verilog
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tb_csprng_fifo.v
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2015-07-18
Read out all data in the fifo by looking at the syn flag. The fifo simulates ok.
Joachim Strömbergson
2015-07-18
Writing a new word into the fifo.
Joachim Strömbergson
2015-07-18
Adding task for reading words from the fifo. Reading out more than 16 words. ↵
Joachim Strömbergson
Refactored w512 task.
2015-07-17
Adding more functionality to observe the fifo during test.
Joachim Strömbergson
2015-07-17
Adding task to dump fifo contents.
Joachim Strömbergson
2015-07-17
Adding more test functionality in the fifo testbench. Now we generates ↵
Joachim Strömbergson
several 512-bit words fed into the fifo.
2015-04-02
(1) Added a state in the write fifo machine to actually drop request between ↵
Joachim Strömbergson
csprng data words. (2) Updated the testbench with better test vector generation.
2015-04-02
Fixed syntax and added init functionality for testing the dut.
Joachim Strömbergson
2015-04-01
Adding initial version of testbench for the csprng fifo.
Joachim Strömbergson