core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Collapse)	Author
2015-12-13	whack copyrights	Paul Selkirk

2015-11-17	Harmonize status valid bit with other cores.	Paul Selkirk

2015-11-16	harmonize ctrl and status addresses with other cores	Paul Selkirk

2015-11-14	Merge branch 'config_core_selector'	Paul Selkirk

2015-10-05	(1) Minor cleanup. Removed unneeded code blocks and comments. (2) Moved ↵	Joachim Strömbergson
	debug mux to below reg updates to match structure in other source files.
2015-10-05	(1) Changed API addresses for ctrl and status registers - HEADSUP: this ↵	Joachim Strömbergson
	might break SW that tries to do discard. Updated core version to reflect api changes. (2) Added support for reading discard and test mode bits in control register.
2015-09-21	Added control FSM states to handle entropy for testing. Nits: Changed to ↵	Joachim Strömbergson
	localparam.
2015-09-07	(1) Debugged the block stat counter. (2) Added missing port type. (3) ↵	Joachim Strömbergson
	Removed second define for default number of blocks.
2015-09-02	Changed the max number of blocks to force reseed once every 256 TByte. ↵	Joachim Strömbergson
	Changed default number of blocks to do reseed once every 16 GByte.
2015-08-20	Adding a stat counter for number of CSPRNG reseeds.	Joachim Strömbergson

2015-07-18	Fixed replication sizes found during lintint.	Joachim Strömbergson

2015-07-18	Simplified the pointer handling. Fixed size of counter. Now all positions in ↵	Joachim Strömbergson
	the fifo is used and flags are correctly set.
2015-06-10	make cores contiguous, add mixer name/version	Paul Selkirk

2015-05-22	(1) Added a cipher block statistics counter. (2) Cleaned up the csprng code ↵	Joachim Strömbergson
	and connected discard for fast restart of trng. (3) Added addresses for allowing API to write a known seed to allow test mode. (3) Fixed a number of minor issues during linting. (4) Fixed the csprng testbench to actually generate data as well as displaying the block stat counter.
2015-04-28	(1) Remove the delayed read for EIM (see core/platform/novena commit ↵	Paul Selkirk
	2f58e8f). (2) Add the code to read the csprng name and version registers.
2015-04-27	Adding name and version fields to the csprng.	Joachim Strömbergson

2015-04-27	Updated the trng version number to sometning that better reflects that it ↵	Joachim Strömbergson
	actually builds and generates values.
2015-04-02	(1) Added a state in the write fifo machine to actually drop request between ↵	Joachim Strömbergson
	csprng data words. (2) Updated the testbench with better test vector generation.
2015-04-01	Cleanup and fixes of calculations.	Joachim Strömbergson

2015-03-26	Minor cleanup: Morged clocked processes. Changed name of api read data hold ↵	Joachim Strömbergson
	register. Changed to localparam. Removed redundant code for reg updates.
2015-03-26	Minor cleanup: Changed to localparam for internal parameters. Merged reg ↵	Joachim Strömbergson
	update processes to one. Changed name of api read data hold reg and added better update vector name for it.
2015-03-26	Changed to Verilog 2001 part select for word extraction.	Joachim Strömbergson

2015-03-26	More cleanup. Completed parameterization of fifo. Fixed incorrect size of ↵	Joachim Strömbergson
	control regs.
2015-03-26	Cleanup from linting. Changing to parameterized fifo pointers. Fixed bug in ↵	Joachim Strömbergson
	bit selection.
2015-03-26	Cleanup: Merged separate clocked processes. Fixed incorrect bit widths. ↵	Joachim Strömbergson
	Changed to localparams. Changed api data read reg to real hold register.
2015-03-25	streamline(?) api_mux, register data for eim output	Paul Selkirk

2014-11-20	Reworked the csprng output fifo to really take advantage of the fact that ↵	Joachim Strömbergson
	the csprng delivers blocks of 512 bits. Removed trailing whitespaces and linted code.
2014-11-20	Updates after linting.	Joachim Strömbergson

2014-11-20	(1) Reducing timepout for entropy sources. Updated interface for sha-512 to ↵	Joachim Strömbergson
	match new interface with work factor ports. We are not using the work factor here at the moment.
2014-10-02	Removing wrappers since they are not used.	Joachim Strömbergson

2014-10-02	Updating trng to debugged version.	Joachim Strömbergson

2014-09-27	Adding debug port for mixer and csprng. In the csprng the debug_update will ↵	Joachim Strömbergson
	trigger fifo extraction and thus force random number generation.
2014-09-26	Updating source to the latest and greatest. In this version the entropy ↵	Joachim Strömbergson
	sources works and all modules have correct intterface.
2014-09-18	Updates after synthesis of the complete trng.	Joachim Strömbergson

2014-09-16	Adding a minor readme to explain when to use the entropy wrappers.	Joachim Strömbergson

2014-09-16	Adding initial version of wrapper for the avalance entropy core to be used ↵	Joachim Strömbergson
	during synthesis.
2014-09-16	Fixed incorrect bit index.	Joachim Strömbergson

2014-09-16	More debug fixes. We add one extra wait cycle to allow the mixer to detect ↵	Joachim Strömbergson
	that we want more seed.
2014-09-16	Debug fixes found during simulation. Now the trng generates data and ↵	Joachim Strömbergson
	provides an api.
2014-09-12	Adding first version of complete trng.	Joachim Strömbergson

2014-09-11	Update after completion of rtl and debug of rtl using the updated testbench. ↵	Joachim Strömbergson
	Now it works.
2014-09-11	Adding initial versions of rtl and tb for the mixer.	Joachim Strömbergson

2014-09-11	Adding rtl and tb for the csprng part of the trng.	Joachim Strömbergson