core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Collapse)	Author
2015-04-02	(1) Added a state in the write fifo machine to actually drop request between ↵	Joachim Strömbergson
	csprng data words. (2) Updated the testbench with better test vector generation.
2015-04-01	Cleanup and fixes of calculations.	Joachim Strömbergson

2015-03-26	Changed to Verilog 2001 part select for word extraction.	Joachim Strömbergson

2015-03-26	More cleanup. Completed parameterization of fifo. Fixed incorrect size of ↵	Joachim Strömbergson
	control regs.
2015-03-26	Cleanup from linting. Changing to parameterized fifo pointers. Fixed bug in ↵	Joachim Strömbergson
	bit selection.
2014-11-20	Reworked the csprng output fifo to really take advantage of the fact that ↵	Joachim Strömbergson
	the csprng delivers blocks of 512 bits. Removed trailing whitespaces and linted code.
2014-09-16	Fixed incorrect bit index.	Joachim Strömbergson

2014-09-11	Adding rtl and tb for the csprng part of the trng.	Joachim Strömbergson