core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Collapse)	Author
2015-06-10	make cores contiguous, add mixer name/version	Paul Selkirk

2015-04-28	(1) Remove the delayed read for EIM (see core/platform/novena commit ↵	Paul Selkirk
	2f58e8f). (2) Add the code to read the csprng name and version registers.
2015-04-27	Updated the trng version number to sometning that better reflects that it ↵	Joachim Strömbergson
	actually builds and generates values.
2015-03-26	Cleanup: Merged separate clocked processes. Fixed incorrect bit widths. ↵	Joachim Strömbergson
	Changed to localparams. Changed api data read reg to real hold register.
2015-03-25	streamline(?) api_mux, register data for eim output	Paul Selkirk

2014-11-20	Updates after linting.	Joachim Strömbergson

2014-10-02	Updating trng to debugged version.	Joachim Strömbergson

2014-09-27	Adding debug port for mixer and csprng. In the csprng the debug_update will ↵	Joachim Strömbergson
	trigger fifo extraction and thus force random number generation.
2014-09-26	Updating source to the latest and greatest. In this version the entropy ↵	Joachim Strömbergson
	sources works and all modules have correct intterface.
2014-09-18	Updates after synthesis of the complete trng.	Joachim Strömbergson

2014-09-16	Debug fixes found during simulation. Now the trng generates data and ↵	Joachim Strömbergson
	provides an api.
2014-09-12	Adding first version of complete trng.	Joachim Strömbergson