core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Expand)	Author
2014-09-26	Removing old fake module for ring oscillator.	Joachim Strömbergson
2014-09-26	Update of fake entropy sources used in simulation.	Joachim Strömbergson
2014-09-18	Updates after synthesis of the complete trng.	Joachim Strömbergson
2014-09-16	Adding implemenatation notes that explains the different models for simulatio...	Joachim Strömbergson
2014-09-16	Adding a minor readme to explain when to use the entropy wrappers.	Joachim Strömbergson
2014-09-16	Adding initial version of wrapper for the avalance entropy core to be used du...	Joachim Strömbergson
2014-09-16	Fixed incorrect bit index.	Joachim Strömbergson
2014-09-16	More debug fixes. We add one extra wait cycle to allow the mixer to detect th...	Joachim Strömbergson
2014-09-16	Debug fixes found during simulation. Now the trng generates data and provides...	Joachim Strömbergson
2014-09-12	Updated Makefile to build the complete trng simulation target.	Joachim Strömbergson
2014-09-12	Adding first version of complete trng.	Joachim Strömbergson
2014-09-12	Adding testbench for the complete trng.	Joachim Strömbergson
2014-09-12	Adding fake modules for the three types of entropy sources to allow us to sim...	Joachim Strömbergson
2014-09-11	Update after completion of rtl and debug of rtl using the updated testbench. ...	Joachim Strömbergson
2014-09-11	Adding initial versions of rtl and tb for the mixer.	Joachim Strömbergson
2014-09-11	Adding compile and sim target for the mixer.	Joachim Strömbergson
2014-09-11	Adding makefile.	Joachim Strömbergson
2014-09-11	Adding rtl and tb for the csprng part of the trng.	Joachim Strömbergson
2014-09-11	Adding readme and license for the trng core.	Joachim Strömbergson