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True Random Number Generator core implemented in Verilog
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2014-09-16
Adding implemenatation notes that explains the different models for ↵
Joachim Strömbergson
simulation and synthesis of the entropy sources.
2014-09-16
Adding a minor readme to explain when to use the entropy wrappers.
Joachim Strömbergson
2014-09-16
Adding initial version of wrapper for the avalance entropy core to be used ↵
Joachim Strömbergson
during synthesis.
2014-09-16
Fixed incorrect bit index.
Joachim Strömbergson
2014-09-16
More debug fixes. We add one extra wait cycle to allow the mixer to detect ↵
Joachim Strömbergson
that we want more seed.
2014-09-16
Debug fixes found during simulation. Now the trng generates data and ↵
Joachim Strömbergson
provides an api.
2014-09-12
Updated Makefile to build the complete trng simulation target.
Joachim Strömbergson
2014-09-12
Adding first version of complete trng.
Joachim Strömbergson
2014-09-12
Adding testbench for the complete trng.
Joachim Strömbergson
2014-09-12
Adding fake modules for the three types of entropy sources to allow us to ↵
Joachim Strömbergson
simulate with known values.
2014-09-11
Update after completion of rtl and debug of rtl using the updated testbench. ↵
Joachim Strömbergson
Now it works.
2014-09-11
Adding initial versions of rtl and tb for the mixer.
Joachim Strömbergson
2014-09-11
Adding compile and sim target for the mixer.
Joachim Strömbergson
2014-09-11
Adding makefile.
Joachim Strömbergson
2014-09-11
Adding rtl and tb for the csprng part of the trng.
Joachim Strömbergson
2014-09-11
Adding readme and license for the trng core.
Joachim Strömbergson