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-rw-r--r--src/rtl/trng.v176
-rw-r--r--src/rtl/trng_csprng.v100
-rw-r--r--src/rtl/trng_mixer.v68
3 files changed, 172 insertions, 172 deletions
diff --git a/src/rtl/trng.v b/src/rtl/trng.v
index e2b9212..7a63f50 100644
--- a/src/rtl/trng.v
+++ b/src/rtl/trng.v
@@ -6,33 +6,33 @@
//
//
// Author: Joachim Strombergson
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2014, SUNET
+// All rights reserved.
//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
//
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
//
-// - Neither the name of the NORDUnet nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
@@ -107,7 +107,7 @@ module trng(
reg [2 : 0] debug_mux_reg;
reg [2 : 0] debug_mux_new;
- reg [2 : 0] debug_mux_we;
+ reg debug_mux_we;
reg [31 : 0] debug_delay_ctr_reg;
reg [31 : 0] debug_delay_ctr_new;
@@ -202,70 +202,70 @@ module trng(
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
- trng_mixer mixer(
- .clk(clk),
- .reset_n(reset_n),
-
- .cs(mixer_api_cs),
- .we(mixer_api_we),
- .address(api_address),
- .write_data(write_data),
- .read_data(mixer_api_read_data),
- .error(mixer_api_error),
-
- .discard(discard_reg),
- .test_mode(test_mode_reg),
- .security_error(mixer_security_error),
-
- .more_seed(csprng_more_seed),
-
- .entropy0_enabled(entropy0_entropy_enabled),
- .entropy0_syn(entropy0_entropy_syn),
- .entropy0_data(entropy0_entropy_data),
- .entropy0_ack(entropy0_entropy_ack),
-
- .entropy1_enabled(entropy1_entropy_enabled),
- .entropy1_syn(entropy1_entropy_syn),
- .entropy1_data(entropy1_entropy_data),
- .entropy1_ack(entropy1_entropy_ack),
-
- .entropy2_enabled(entropy2_entropy_enabled),
- .entropy2_syn(entropy2_entropy_syn),
- .entropy2_data(entropy2_entropy_data),
- .entropy2_ack(entropy2_entropy_ack),
-
- .seed_data(mixer_seed_data),
- .seed_syn(mixer_seed_syn),
- .seed_ack(csprng_seed_ack),
-
- .debug(mixer_debug),
- .debug_update(mixer_debug_update)
- );
-
- trng_csprng csprng(
- .clk(clk),
- .reset_n(reset_n),
-
- .cs(csprng_api_cs),
- .we(csprng_api_we),
- .address(api_address),
- .write_data(write_data),
- .read_data(csprng_api_read_data),
- .error(csprng_api_error),
-
- .discard(discard_reg),
- .test_mode(test_mode_reg),
- .security_error(csprng_security_error),
-
- .more_seed(csprng_more_seed),
-
- .seed_data(mixer_seed_data),
- .seed_syn(mixer_seed_syn),
- .seed_ack(csprng_seed_ack),
-
- .debug(csprng_debug),
- .debug_update(csprng_debug_update)
- );
+ trng_mixer mixer_inst(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .cs(mixer_api_cs),
+ .we(mixer_api_we),
+ .address(api_address),
+ .write_data(write_data),
+ .read_data(mixer_api_read_data),
+ .error(mixer_api_error),
+
+ .discard(discard_reg),
+ .test_mode(test_mode_reg),
+ .security_error(mixer_security_error),
+
+ .more_seed(csprng_more_seed),
+
+ .entropy0_enabled(entropy0_entropy_enabled),
+ .entropy0_syn(entropy0_entropy_syn),
+ .entropy0_data(entropy0_entropy_data),
+ .entropy0_ack(entropy0_entropy_ack),
+
+ .entropy1_enabled(entropy1_entropy_enabled),
+ .entropy1_syn(entropy1_entropy_syn),
+ .entropy1_data(entropy1_entropy_data),
+ .entropy1_ack(entropy1_entropy_ack),
+
+ .entropy2_enabled(entropy2_entropy_enabled),
+ .entropy2_syn(entropy2_entropy_syn),
+ .entropy2_data(entropy2_entropy_data),
+ .entropy2_ack(entropy2_entropy_ack),
+
+ .seed_data(mixer_seed_data),
+ .seed_syn(mixer_seed_syn),
+ .seed_ack(csprng_seed_ack),
+
+ .debug(mixer_debug),
+ .debug_update(mixer_debug_update)
+ );
+
+ trng_csprng csprng_inst(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .cs(csprng_api_cs),
+ .we(csprng_api_we),
+ .address(api_address),
+ .write_data(write_data),
+ .read_data(csprng_api_read_data),
+ .error(csprng_api_error),
+
+ .discard(discard_reg),
+ .test_mode(test_mode_reg),
+ .security_error(csprng_security_error),
+
+ .more_seed(csprng_more_seed),
+
+ .seed_data(mixer_seed_data),
+ .seed_syn(mixer_seed_syn),
+ .seed_ack(csprng_seed_ack),
+
+ .debug(csprng_debug),
+ .debug_update(csprng_debug_update)
+ );
avalanche_entropy entropy1(
.clk(clk),
diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v
index c4576e8..f985be4 100644
--- a/src/rtl/trng_csprng.v
+++ b/src/rtl/trng_csprng.v
@@ -6,33 +6,33 @@
//
//
// Author: Joachim Strombergson
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2014, SUNET
+// All rights reserved.
//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
//
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
//
-// - Neither the name of the NORDUnet nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
@@ -198,40 +198,40 @@ module trng_csprng(
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
- chacha_core cipher(
- .clk(clk),
- .reset_n(reset_n),
+ chacha_core cipher_inst(
+ .clk(clk),
+ .reset_n(reset_n),
- .init(cipher_init),
- .next(cipher_next),
+ .init(cipher_init),
+ .next(cipher_next),
- .key(cipher_key_reg),
- .keylen(CIPHER_KEYLEN256),
- .iv(cipher_iv_reg),
- .ctr(cipher_ctr_reg),
- .rounds(num_rounds_reg),
+ .key(cipher_key_reg),
+ .keylen(CIPHER_KEYLEN256),
+ .iv(cipher_iv_reg),
+ .ctr(cipher_ctr_reg),
+ .rounds(num_rounds_reg),
- .data_in(cipher_block_reg),
- .ready(cipher_ready),
+ .data_in(cipher_block_reg),
+ .ready(cipher_ready),
- .data_out(cipher_data_out),
- .data_out_valid(cipher_data_out_valid)
- );
+ .data_out(cipher_data_out),
+ .data_out_valid(cipher_data_out_valid)
+ );
- trng_csprng_fifo fifo(
- .clk(clk),
- .reset_n(reset_n),
+ trng_csprng_fifo fifo_inst(
+ .clk(clk),
+ .reset_n(reset_n),
- .csprng_data(cipher_data_out),
- .csprng_data_valid(fifo_cipher_data_valid),
- .discard(fifo_discard),
- .more_data(fifo_more_data),
+ .csprng_data(cipher_data_out),
+ .csprng_data_valid(fifo_cipher_data_valid),
+ .discard(fifo_discard),
+ .more_data(fifo_more_data),
- .rnd_syn(rnd_syn),
- .rnd_data(rnd_data),
- .rnd_ack(muxed_rnd_ack)
- );
+ .rnd_syn(rnd_syn),
+ .rnd_data(rnd_data),
+ .rnd_ack(muxed_rnd_ack)
+ );
//----------------------------------------------------------------
@@ -397,7 +397,7 @@ module trng_csprng(
ADDR_STATUS:
begin
- tmp_read_data = {ready_reg, rnd_syn};
+ tmp_read_data = {30'h00000000, ready_reg, rnd_syn};
end
ADDR_RND_DATA:
diff --git a/src/rtl/trng_mixer.v b/src/rtl/trng_mixer.v
index 455d15c..de57fe0 100644
--- a/src/rtl/trng_mixer.v
+++ b/src/rtl/trng_mixer.v
@@ -110,69 +110,69 @@ module trng_mixer(
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] block00_reg;
- reg [31 : 0] block00_we;
+ reg block00_we;
reg [31 : 0] block01_reg;
- reg [31 : 0] block01_we;
+ reg block01_we;
reg [31 : 0] block02_reg;
- reg [31 : 0] block02_we;
+ reg block02_we;
reg [31 : 0] block03_reg;
- reg [31 : 0] block03_we;
+ reg block03_we;
reg [31 : 0] block04_reg;
- reg [31 : 0] block04_we;
+ reg block04_we;
reg [31 : 0] block05_reg;
- reg [31 : 0] block05_we;
+ reg block05_we;
reg [31 : 0] block06_reg;
- reg [31 : 0] block06_we;
+ reg block06_we;
reg [31 : 0] block07_reg;
- reg [31 : 0] block07_we;
+ reg block07_we;
reg [31 : 0] block08_reg;
- reg [31 : 0] block08_we;
+ reg block08_we;
reg [31 : 0] block09_reg;
- reg [31 : 0] block09_we;
+ reg block09_we;
reg [31 : 0] block10_reg;
- reg [31 : 0] block10_we;
+ reg block10_we;
reg [31 : 0] block11_reg;
- reg [31 : 0] block11_we;
+ reg block11_we;
reg [31 : 0] block12_reg;
- reg [31 : 0] block12_we;
+ reg block12_we;
reg [31 : 0] block13_reg;
- reg [31 : 0] block13_we;
+ reg block13_we;
reg [31 : 0] block14_reg;
- reg [31 : 0] block14_we;
+ reg block14_we;
reg [31 : 0] block15_reg;
- reg [31 : 0] block15_we;
+ reg block15_we;
reg [31 : 0] block16_reg;
- reg [31 : 0] block16_we;
+ reg block16_we;
reg [31 : 0] block17_reg;
- reg [31 : 0] block17_we;
+ reg block17_we;
reg [31 : 0] block18_reg;
- reg [31 : 0] block18_we;
+ reg block18_we;
reg [31 : 0] block19_reg;
- reg [31 : 0] block19_we;
+ reg block19_we;
reg [31 : 0] block20_reg;
- reg [31 : 0] block20_we;
+ reg block20_we;
reg [31 : 0] block21_reg;
- reg [31 : 0] block21_we;
+ reg block21_we;
reg [31 : 0] block22_reg;
- reg [31 : 0] block22_we;
+ reg block22_we;
reg [31 : 0] block23_reg;
- reg [31 : 0] block23_we;
+ reg block23_we;
reg [31 : 0] block24_reg;
- reg [31 : 0] block24_we;
+ reg block24_we;
reg [31 : 0] block25_reg;
- reg [31 : 0] block25_we;
+ reg block25_we;
reg [31 : 0] block26_reg;
- reg [31 : 0] block26_we;
+ reg block26_we;
reg [31 : 0] block27_reg;
- reg [31 : 0] block27_we;
+ reg block27_we;
reg [31 : 0] block28_reg;
- reg [31 : 0] block28_we;
+ reg block28_we;
reg [31 : 0] block29_reg;
- reg [31 : 0] block29_we;
+ reg block29_we;
reg [31 : 0] block30_reg;
- reg [31 : 0] block30_we;
+ reg block30_we;
reg [31 : 0] block31_reg;
- reg [31 : 0] block31_we;
+ reg block31_we;
reg [4 : 0] word_ctr_reg;
reg [4 : 0] word_ctr_new;
@@ -604,7 +604,7 @@ module trng_mixer(
// Read operations.
ADDR_MIXER_CTRL:
begin
- tmp_read_data = {restart_reg, enable_reg};
+ tmp_read_data = {30'h00000000, restart_reg, enable_reg};
end
ADDR_MIXER_STATUS:
@@ -614,7 +614,7 @@ module trng_mixer(
ADDR_MIXER_TIMEOUT:
begin
- tmp_read_data = entropy_timeout_reg;
+ tmp_read_data = {8'h00, entropy_timeout_reg};
end
default: