diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/rtl/trng_csprng_fifo.v | 83 |
1 files changed, 36 insertions, 47 deletions
diff --git a/src/rtl/trng_csprng_fifo.v b/src/rtl/trng_csprng_fifo.v index b6ff2c1..19539d9 100644 --- a/src/rtl/trng_csprng_fifo.v +++ b/src/rtl/trng_csprng_fifo.v @@ -55,17 +55,18 @@ module trng_csprng_fifo( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - parameter FIFO_DEPTH = 4; - parameter FIFO_MAX = FIFO_DEPTH - 1; + localparam FIFO_ADDR_BITS = 2; + localparam FIFO_ADDR_MAX = FIFO_ADDR_BITS - 1; + localparam FIFO_MAX = (2 >> FIFO_ADDR_BITS) - 1; - parameter WR_IDLE = 0; - parameter WR_WAIT = 1; - parameter WR_WRITE = 2; - parameter WR_DISCARD = 7; + localparam WR_IDLE = 0; + localparam WR_WAIT = 1; + localparam WR_WRITE = 2; + localparam WR_DISCARD = 7; - parameter RD_IDLE = 0; - parameter RD_ACK = 1; - parameter RD_DISCARD = 7; + localparam RD_IDLE = 0; + localparam RD_ACK = 1; + localparam RD_DISCARD = 7; //---------------------------------------------------------------- @@ -80,14 +81,14 @@ module trng_csprng_fifo( reg mux_data_ptr_rst; reg mux_data_ptr_we; - reg [2 : 0] wr_ptr_reg; - reg [2 : 0] wr_ptr_new; + reg [1 : 0] wr_ptr_reg; + reg [1 : 0] wr_ptr_new; reg wr_ptr_inc; reg wr_ptr_rst; reg wr_ptr_we; - reg [2 : 0] rd_ptr_reg; - reg [2 : 0] rd_ptr_new; + reg [1 : 0] rd_ptr_reg; + reg [1 : 0] rd_ptr_new; reg rd_ptr_inc; reg rd_ptr_rst; reg rd_ptr_we; @@ -98,13 +99,13 @@ module trng_csprng_fifo( reg rnd_syn_new; reg rnd_syn_we; - reg [2 : 0] wr_ctrl_reg; - reg [2 : 0] wr_ctrl_new; - reg wr_ctrl_we; + reg [FIFO_ADDR_MAX : 0] rd_ctrl_reg; + reg [FIFO_ADDR_MAX : 0] rd_ctrl_new; + reg rd_ctrl_we; - reg [2 : 0] rd_ctrl_reg; - reg [2 : 0] rd_ctrl_new; - reg rd_ctrl_we; + reg [FIFO_ADDR_MAX : 0] wr_ctrl_reg; + reg [FIFO_ADDR_MAX : 0] wr_ctrl_new; + reg wr_ctrl_we; reg [2 : 0] fifo_ctr_reg; reg [2 : 0] fifo_ctr_new; @@ -147,8 +148,8 @@ module trng_csprng_fifo( fifo_mem[02] <= {16{32'h00000000}}; fifo_mem[03] <= {16{32'h00000000}}; mux_data_ptr_reg <= 4'h0; - wr_ptr_reg <= 3'h0; - rd_ptr_reg <= 3'h0; + rd_ptr_reg <= {FIFO_ADDR_BITS{1'b0}}; + wr_ptr_reg <= {FIFO_ADDR_BITS{1'b0}}; fifo_ctr_reg <= 3'h0; rnd_data_reg <= 32'h00000000; rnd_syn_reg <= 0; @@ -176,14 +177,14 @@ module trng_csprng_fifo( mux_data_ptr_reg <= mux_data_ptr_new; end - if (wr_ptr_we) + if (rd_ptr_we) begin - wr_ptr_reg <= wr_ptr_new; + rd_ptr_reg <= rd_ptr_new; end - if (rd_ptr_we) + if (wr_ptr_we) begin - rd_ptr_reg <= rd_ptr_new; + wr_ptr_reg <= wr_ptr_new; end if (fifo_ctr_we) @@ -226,7 +227,7 @@ module trng_csprng_fifo( 06: muxed_data = fifo_rd_data[223 : 192]; 07: muxed_data = fifo_rd_data[255 : 224]; 08: muxed_data = fifo_rd_data[287 : 256]; - 09: muxed_data = fifo_rd_data[313 : 282]; + 09: muxed_data = fifo_rd_data[319 : 288]; 10: muxed_data = fifo_rd_data[351 : 320]; 11: muxed_data = fifo_rd_data[383 : 352]; 12: muxed_data = fifo_rd_data[415 : 384]; @@ -270,24 +271,18 @@ module trng_csprng_fifo( //---------------------------------------------------------------- always @* begin : fifo_rd_ptr - rd_ptr_new = 3'h0; + rd_ptr_new = {FIFO_ADDR_BITS{1'b0}}; rd_ptr_we = 0; fifo_ctr_dec = 0; if (rd_ptr_rst) - begin - rd_ptr_new = 3'h0; - rd_ptr_we = 1; - end + rd_ptr_we = 1; if (rd_ptr_inc) begin fifo_ctr_dec = 1; - if (rd_ptr_reg == FIFO_MAX) - begin - rd_ptr_new = 3'h0; - rd_ptr_we = 1; - end + if (rd_ptr_reg == FIFO_ADDR_MAX) + rd_ptr_we = 1; else begin rd_ptr_new = rd_ptr_reg + 1'b1; @@ -304,22 +299,16 @@ module trng_csprng_fifo( //---------------------------------------------------------------- always @* begin : fifo_wr_ptr - wr_ptr_new = 3'h0; - wr_ptr_we = 0; + wr_ptr_new = {FIFO_ADDR_BITS{1'b0}}; + wr_ptr_we = 0; if (wr_ptr_rst) - begin - wr_ptr_new = 3'h0; - wr_ptr_we = 1; - end + wr_ptr_we = 1; if (wr_ptr_inc) begin - if (wr_ptr_reg == FIFO_MAX) - begin - wr_ptr_new = 3'h0; - wr_ptr_we = 1; - end + if (wr_ptr_reg == FIFO_ADDR_MAX) + wr_ptr_we = 1; else begin wr_ptr_new = wr_ptr_reg + 1'b1; |