diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/rtl/trng_csprng_fifo.v | 17 | ||||
| -rw-r--r-- | src/tb/tb_csprng_fifo.v | 12 |
2 files changed, 17 insertions, 12 deletions
diff --git a/src/rtl/trng_csprng_fifo.v b/src/rtl/trng_csprng_fifo.v index e4abc26..9c52ef5 100644 --- a/src/rtl/trng_csprng_fifo.v +++ b/src/rtl/trng_csprng_fifo.v @@ -60,8 +60,7 @@ module trng_csprng_fifo( localparam FIFO_MAX = (2 ** FIFO_ADDR_BITS) - 1; localparam WR_IDLE = 0; - localparam WR_WAIT = 1; - localparam WR_WRITE = 2; + localparam WR_STORE = 1; localparam WR_DISCARD = 7; localparam RD_IDLE = 0; @@ -453,13 +452,21 @@ module trng_csprng_fifo( if (csprng_data_valid) begin - fifo_mem_we = 1; - wr_ptr_inc = 1; - fifo_ctr_inc = 1; + wr_ctrl_new = WR_STORE; + wr_ctrl_we = 1; end end end + WR_STORE: + begin + fifo_mem_we = 1; + wr_ptr_inc = 1; + fifo_ctr_inc = 1; + wr_ctrl_new = WR_IDLE; + wr_ctrl_we = 1; + end + WR_DISCARD: begin fifo_ctr_rst = 1; diff --git a/src/tb/tb_csprng_fifo.v b/src/tb/tb_csprng_fifo.v index c5e283e..91044a5 100644 --- a/src/tb/tb_csprng_fifo.v +++ b/src/tb/tb_csprng_fifo.v @@ -81,7 +81,8 @@ module tb_csprng_fifo(); wire [31 : 0] tb_rnd_data; reg tb_rnd_ack; - integer i; + reg [7 : 0] i; + //---------------------------------------------------------------- // Device Under Test. @@ -158,7 +159,7 @@ module tb_csprng_fifo(); always @ (posedge tb_more_data) begin for (i = 0 ; i < 16 ; i = i + 1) - tb_csprng_data[i * 32 +: 32] = ~tb_csprng_data[i * 32 +: 32] + 32'h01010101; + tb_csprng_data[i * 32 +: 32] = tb_csprng_data[i * 32 +: 32] + 32'h10101010; tb_csprng_data_valid = 1'b1; #(2 * CLK_PERIOD); @@ -210,8 +211,6 @@ module tb_csprng_fifo(); // as setting the DUT inputs to defined values. //---------------------------------------------------------------- task init_sim(); - integer i; - begin cycle_ctr = 0; error_ctr = 0; @@ -229,8 +228,7 @@ module tb_csprng_fifo(); tb_rnd_ack = 1; for (i = 0 ; i < 16 ; i = i + 1) - tb_csprng_data[i * 32 +: 32] = 32'h01010101 << (i + 1); - + tb_csprng_data[i * 32 +: 32] = {i, i, i, i}; end endtask // init_sim @@ -252,7 +250,7 @@ module tb_csprng_fifo(); reset_dut(); dump_dut_state(); - #(100000 * CLK_PERIOD) + #(100 * CLK_PERIOD) display_test_results(); |