aboutsummaryrefslogtreecommitdiff
path: root/src/tb
diff options
context:
space:
mode:
Diffstat (limited to 'src/tb')
-rw-r--r--src/tb/tb_csprng.v105
-rw-r--r--src/tb/tb_csprng_fifo.v199
2 files changed, 277 insertions, 27 deletions
diff --git a/src/tb/tb_csprng.v b/src/tb/tb_csprng.v
index 0404b56..bd84489 100644
--- a/src/tb/tb_csprng.v
+++ b/src/tb/tb_csprng.v
@@ -50,7 +50,7 @@ module tb_csprng();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
- parameter DEBUG = 1;
+ parameter DEBUG = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
@@ -68,6 +68,7 @@ module tb_csprng();
localparam ADDR_STAT_BLOCKS_LOW = 8'h14;
localparam ADDR_STAT_BLOCKS_HIGH = 8'h15;
+ localparam ADDR_STAT_RESEEDS = 8'h16;
localparam ADDR_RND_DATA = 8'h20;
@@ -109,6 +110,7 @@ module tb_csprng();
reg tb_debug_update;
reg [31 : 0] read_data;
+ reg [7 : 0] pbyte;
//----------------------------------------------------------------
@@ -127,10 +129,9 @@ module tb_csprng();
.discard(tb_discard),
.test_mode(tb_test_mode),
-
- .more_seed(tb_more_seed),
.security_error(tb_security_error),
+ .more_seed(tb_more_seed),
.seed_data(tb_seed_data),
.seed_syn(tb_seed_syn),
.seed_ack(tb_seed_ack),
@@ -210,11 +211,6 @@ module tb_csprng();
dut.cipher_inst.ready, dut.cipher_inst.data_out_valid);
$display("cipher data out: 0x%064x", dut.cipher_inst.data_out);
$display("");
-
- $display("Outputs:");
- $display("rnd_syn = 0x%01x, rnd_ack = 0x%01x, rnd_data = 0x%08x",
- dut.rnd_syn, dut.rnd_ack, tb_read_data);
- $display("");
end
endtask // dump_dut_state
@@ -237,6 +233,7 @@ module tb_csprng();
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
+
#(2 * CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
@@ -330,14 +327,68 @@ module tb_csprng();
tb_test_mode = 0;
tb_seed_syn = 0;
- tb_seed_data = {16{32'h00000000}};
+ tb_seed_data = {8{64'h0000000000000000}};
tb_rnd_ack = 0;
tb_debug_update = 0;
+
+ pbyte = 8'h00;
end
endtask // init_sim
//----------------------------------------------------------------
+ // seed_generator
+ //
+ // When a seed_syn is observed this process will provide a new
+ // seed to the DUT, assert SYN, wait for ACK and then update
+ // the seed pattern state.
+ //----------------------------------------------------------------
+ always @ (posedge tb_more_seed)
+ begin : seed_generator
+ #(CLK_PERIOD);
+ tb_seed_data = {64{pbyte}};
+ tb_seed_syn = 1'b1;
+
+ while (!tb_seed_ack)
+ #(CLK_PERIOD);
+
+ tb_seed_syn = 1'b0;
+ pbyte = pbyte + 8'h01;
+ end
+
+
+ //----------------------------------------------------------------
+ // read_rng_data()
+ //
+ // Support task that reads a given number of data words
+ // from the DUT via the API.
+ //----------------------------------------------------------------
+ task read_rng_data(input [31 : 0] num_words);
+ reg [31 : 0] i;
+ begin
+ i = 32'h00000000;
+
+ $display("*** Trying to read 0x%08x RNG data words", num_words);
+ while (i < num_words)
+ begin
+ tb_cs = 1'b1;
+ tb_we = 1'b0;
+ tb_address = ADDR_RND_DATA;
+ i = i + 1;
+
+ #CLK_PERIOD;
+
+ if (DEBUG)
+ $display("*** RNG data word 0x%08x: 0x%08x", i, tb_read_data);
+ end
+
+ tb_cs = 1'b0;
+ $display("*** Reading of RNG data words completed.");
+ end
+ endtask // read_rng_data
+
+
+ //----------------------------------------------------------------
// tc1_init_csprng()
//
// TC1: Test that the DUT automatically starts initialize when
@@ -353,11 +404,8 @@ module tb_csprng();
tb_seed_data = {8{64'haaaaaaaa55555555}};
tb_seed_syn = 1'b1;
- tb_cs = 1'b1;
- tb_we = 1'b0;
- tb_address = ADDR_RND_DATA;
-
- #(200 * CLK_PERIOD);
+ // Start pulling data.
+ read_rng_data(32'h100);
$display("*** TC1: Test automatic init of csprng done.");
end
@@ -365,6 +413,32 @@ module tb_csprng();
//----------------------------------------------------------------
+ // tc2_reseed_csprng()
+ //
+ // TC2: Test that the CSPRNG is reseeded as expected.
+ // We set the max block size to a small value and pull data.
+ //----------------------------------------------------------------
+ task tc2_reseed_csprng();
+ begin
+ tc_ctr = tc_ctr + 1;
+
+ $display("*** TC2: Test reseed of CSPRNG started.");
+
+ tb_seed_data = {8{64'h0102030405060708}};
+ tb_seed_syn = 1'b1;
+
+ // Set the max number of blocks to a low value
+ write_word(ADDR_NUM_BLOCKS_HIGH, 32'h00000000);
+ write_word(ADDR_NUM_BLOCKS_LOW, 32'h00000007);
+
+ read_rng_data(32'h10000);
+
+ $display("*** TC2 done..");
+ end
+ endtask // tc2_reseed_csprng
+
+
+ //----------------------------------------------------------------
// csprng_test
//
// The main test functionality.
@@ -381,7 +455,8 @@ module tb_csprng();
reset_dut();
dump_dut_state();
- tc1_init_csprng();
+// tc1_init_csprng();
+ tc2_reseed_csprng();
display_test_results();
diff --git a/src/tb/tb_csprng_fifo.v b/src/tb/tb_csprng_fifo.v
index 91044a5..a2db466 100644
--- a/src/tb/tb_csprng_fifo.v
+++ b/src/tb/tb_csprng_fifo.v
@@ -50,7 +50,7 @@ module tb_csprng_fifo();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
- parameter DEBUG = 1;
+ parameter DEBUG = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
@@ -143,9 +143,39 @@ module tb_csprng_fifo();
$display("cycle: 0x%016x", cycle_ctr);
$display("State of DUT");
$display("------------");
+ $display("inputs:");
+ $display("more_data = 0x%01x, data_valid = 0x%01x",
+ tb_more_data, tb_csprng_data_valid);
+ $display("input_data = 0x%0128x", tb_csprng_data);
+ $display("");
+ $display("outputs:");
$display("rnd_syn = 0x%01x, rnd_ack = 0x%01x, rnd_data = 0x%08x",
tb_rnd_syn, tb_rnd_ack, tb_rnd_data);
$display("");
+ $display("internals:");
+ $display("rd_ptr = 0x%02x, wr_ptr = 0x%02x, fifo_ctr = 0x%02x, mux_ptr = 0x%02x",
+ dut.rd_ptr_reg, dut.wr_ptr_reg, dut.fifo_ctr_reg, dut.mux_data_ptr_reg);
+ $display("fifo_empty = 0x%01x, fifo_full = 0x%01x", dut.fifo_empty, dut.fifo_full);
+ $display("");
+ end
+ endtask // dump_dut_state
+
+
+ //----------------------------------------------------------------
+ // dump_fifo()
+ //
+ // Dump the state of the fifo when needed.
+ //----------------------------------------------------------------
+ task dump_fifo();
+ begin
+ $display("contents of the fifo");
+ $display("--------------------");
+ $display("fifo_mem[0] = 0x%0128x", dut.fifo_mem[0]);
+ $display("fifo_mem[1] = 0x%0128x", dut.fifo_mem[1]);
+ $display("fifo_mem[2] = 0x%0128x", dut.fifo_mem[2]);
+ $display("fifo_mem[3] = 0x%0128x", dut.fifo_mem[3]);
+ $display("");
+ $display("");
end
endtask // dump_dut_state
@@ -156,15 +186,15 @@ module tb_csprng_fifo();
// Generate test data with distinct patterns as requested
// by the dut.
//----------------------------------------------------------------
- always @ (posedge tb_more_data)
- begin
- for (i = 0 ; i < 16 ; i = i + 1)
- tb_csprng_data[i * 32 +: 32] = tb_csprng_data[i * 32 +: 32] + 32'h10101010;
-
- tb_csprng_data_valid = 1'b1;
- #(2 * CLK_PERIOD);
- tb_csprng_data_valid = 1'b0;
- end
+// always @ (posedge tb_more_data)
+// begin
+// for (i = 0 ; i < 16 ; i = i + 1)
+// tb_csprng_data[i * 32 +: 32] = tb_csprng_data[i * 32 +: 32] + 32'h10101010;
+//
+// tb_csprng_data_valid = 1'b1;
+// #(2 * CLK_PERIOD);
+// tb_csprng_data_valid = 1'b0;
+// end
//----------------------------------------------------------------
@@ -225,15 +255,156 @@ module tb_csprng_fifo();
tb_write_data = 32'h00000000;
tb_discard = 0;
- tb_rnd_ack = 1;
+ tb_rnd_ack = 0;
for (i = 0 ; i < 16 ; i = i + 1)
- tb_csprng_data[i * 32 +: 32] = {i, i, i, i};
+ tb_csprng_data[i * 32 +: 32] = 32'h0;
+ tb_csprng_data_valid = 0;
end
endtask // init_sim
//----------------------------------------------------------------
+ // wait_more_data()
+ //
+ // Wait for the DUT to signal that it wants more data.
+ //----------------------------------------------------------------
+ task wait_more_data();
+ begin
+ while (!tb_more_data)
+ #(CLK_PERIOD);
+ end
+ endtask // wait_more_data
+
+
+ //----------------------------------------------------------------
+ // write_w512()
+ //
+ // Writes a 512 bit data word into the fifo.
+ //----------------------------------------------------------------
+ task write_w512(input [7 : 0] b);
+ reg [511 : 0] w512;
+ reg [31 : 0] w00;
+ reg [31 : 0] w01;
+ reg [31 : 0] w02;
+ reg [31 : 0] w03;
+ reg [31 : 0] w04;
+ reg [31 : 0] w05;
+ reg [31 : 0] w06;
+ reg [31 : 0] w07;
+ reg [31 : 0] w08;
+ reg [31 : 0] w09;
+ reg [31 : 0] w10;
+ reg [31 : 0] w11;
+ reg [31 : 0] w12;
+ reg [31 : 0] w13;
+ reg [31 : 0] w14;
+ reg [31 : 0] w15;
+ begin
+ w00 = {(b + 8'd15), (b + 8'd15), (b + 8'd15), (b + 8'd15)};
+ w01 = {(b + 8'd14), (b + 8'd14), (b + 8'd14), (b + 8'd14)};
+ w02 = {(b + 8'd13), (b + 8'd13), (b + 8'd13), (b + 8'd13)};
+ w03 = {(b + 8'd12), (b + 8'd12), (b + 8'd12), (b + 8'd12)};
+ w04 = {(b + 8'd11), (b + 8'd11), (b + 8'd11), (b + 8'd11)};
+ w05 = {(b + 8'd10), (b + 8'd10), (b + 8'd10), (b + 8'd10)};
+ w06 = {(b + 8'd09), (b + 8'd09), (b + 8'd09), (b + 8'd09)};
+ w07 = {(b + 8'd08), (b + 8'd08), (b + 8'd08), (b + 8'd08)};
+
+ w08 = {(b + 8'd07), (b + 8'd07), (b + 8'd07), (b + 8'd07)};
+ w09 = {(b + 8'd06), (b + 8'd06), (b + 8'd06), (b + 8'd06)};
+ w10 = {(b + 8'd05), (b + 8'd05), (b + 8'd05), (b + 8'd05)};
+ w11 = {(b + 8'd04), (b + 8'd04), (b + 8'd04), (b + 8'd04)};
+ w12 = {(b + 8'd03), (b + 8'd03), (b + 8'd03), (b + 8'd03)};
+ w13 = {(b + 8'd02), (b + 8'd02), (b + 8'd02), (b + 8'd02)};
+ w14 = {(b + 8'd01), (b + 8'd01), (b + 8'd01), (b + 8'd01)};
+ w15 = {(b + 8'd00), (b + 8'd00), (b + 8'd00), (b + 8'd00)};
+
+ w512 = {w00, w01, w02, w03, w04, w05, w06, w07,
+ w08, w09, w10, w11, w12, w13, w14, w15};
+
+ wait_more_data();
+
+ dump_dut_state();
+ dump_fifo();
+
+ $display("writing to fifo: 0x%0128x", w512);
+ tb_csprng_data = w512;
+ tb_csprng_data_valid = 1;
+ #(CLK_PERIOD);
+ tb_csprng_data_valid = 0;
+ end
+ endtask // write_w512
+
+
+ //----------------------------------------------------------------
+ // read_w32()
+ //
+ // read a 32 bit data word from the fifo.
+ //----------------------------------------------------------------
+ task read_w32();
+ begin
+ $display("*** Reading from the fifo: 0x%08x", tb_rnd_data);
+ tb_rnd_ack = 1;
+ #(2 * CLK_PERIOD);
+ tb_rnd_ack = 0;
+ dump_dut_state();
+ end
+ endtask // read_w32
+
+
+ //----------------------------------------------------------------
+ // fifo_test()
+ //
+ // Writes a number of 512-bit words to the FIFO and then
+ // extracts 32-bit words and checks that we get the correct
+ // words all the time.
+ //----------------------------------------------------------------
+ task fifo_test();
+ reg [7 : 0] i;
+ reg [7 : 0] j;
+
+ begin
+ $display("*** Test of FIFO by loading known data and then reading out.");
+
+ dump_dut_state();
+ dump_fifo();
+
+ i = 8'd0;
+
+ // Filling up the memory with data.
+ for (j = 0 ; j < 4 ; j = j + 1)
+ begin
+ write_w512(i);
+ #(2 * CLK_PERIOD);
+ i = i + 16;
+ end
+
+ dump_dut_state();
+ dump_fifo();
+
+ // Read out a number of words from the fifo.
+ for (j = 0 ; j < 17 ; j = j + 1)
+ begin
+ read_w32();
+ end
+
+ dump_dut_state();
+ dump_fifo();
+
+ // Write another 512-bit word into the fifo.
+ write_w512(8'h40);
+
+
+ // Read out all of the rest of the data.
+ while (tb_rnd_syn)
+ read_w32();
+
+ dump_fifo();
+ end
+ endtask // fifo_test
+
+
+ //----------------------------------------------------------------
// csprng_test
//
// The main test functionality.
@@ -250,6 +421,10 @@ module tb_csprng_fifo();
reset_dut();
dump_dut_state();
+ #(10 * CLK_PERIOD)
+
+ fifo_test();
+
#(100 * CLK_PERIOD)
display_test_results();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 11:33:28 +0000