diff options
Diffstat (limited to 'src/tb')
| -rw-r--r-- | src/tb/tb_csprng_fifo.v | 37 |
1 files changed, 35 insertions, 2 deletions
diff --git a/src/tb/tb_csprng_fifo.v b/src/tb/tb_csprng_fifo.v index 8b01ce0..a219dfe 100644 --- a/src/tb/tb_csprng_fifo.v +++ b/src/tb/tb_csprng_fifo.v @@ -50,7 +50,7 @@ module tb_csprng_fifo(); //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - parameter DEBUG = 1; + parameter DEBUG = 0; parameter CLK_HALF_PERIOD = 1; parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; @@ -161,6 +161,26 @@ module tb_csprng_fifo(); //---------------------------------------------------------------- + // dump_fifo() + // + // Dump the state of the fifo when needed. + //---------------------------------------------------------------- + task dump_fifo(); + begin + $display("contents of the fifo"); + $display("--------------------"); + $display("inputs:"); + $display("fifo_mem[0] = 0x%0128x", dut.fifo_mem[0]); + $display("fifo_mem[1] = 0x%0128x", dut.fifo_mem[1]); + $display("fifo_mem[2] = 0x%0128x", dut.fifo_mem[2]); + $display("fifo_mem[3] = 0x%0128x", dut.fifo_mem[3]); + $display(""); + $display(""); + end + endtask // dump_dut_state + + + //---------------------------------------------------------------- // gen_csprng_data // // Generate test data with distinct patterns as requested @@ -240,7 +260,6 @@ module tb_csprng_fifo(); for (i = 0 ; i < 16 ; i = i + 1) tb_csprng_data[i * 32 +: 32] = 32'h0; tb_csprng_data_valid = 0; - end endtask // init_sim @@ -252,10 +271,18 @@ module tb_csprng_fifo(); //---------------------------------------------------------------- task write_w512(input [511 : 0] w512); begin + while (!tb_more_data) + begin + #(CLK_PERIOD); + end + + $display("writing to fifo: 0x%0128x", w512); + dump_dut_state(); tb_csprng_data = w512; tb_csprng_data_valid = 1; #(CLK_PERIOD); tb_csprng_data_valid = 0; + dump_dut_state(); end endtask // write_w512 @@ -289,6 +316,8 @@ module tb_csprng_fifo(); reg [31 : 0] w15; begin + dump_fifo(); + i = 8'd0; // Filling up the memory with data. @@ -316,8 +345,12 @@ module tb_csprng_fifo(); w08, w09, w10, w11, w12, w13, w14, w15}; write_w512(w512); + #(CLK_PERIOD); i = i + 16; end + + dump_fifo(); + end endtask // init_sim |