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Diffstat (limited to 'src/tb/tb_csprng_fifo.v')
-rw-r--r--src/tb/tb_csprng_fifo.v38
1 files changed, 8 insertions, 30 deletions
diff --git a/src/tb/tb_csprng_fifo.v b/src/tb/tb_csprng_fifo.v
index a2db466..db598f5 100644
--- a/src/tb/tb_csprng_fifo.v
+++ b/src/tb/tb_csprng_fifo.v
@@ -36,11 +36,6 @@
//
//======================================================================
-//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
//------------------------------------------------------------------
// Test module.
@@ -138,7 +133,7 @@ module tb_csprng_fifo();
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
- task dump_dut_state();
+ task dump_dut_state;
begin
$display("cycle: 0x%016x", cycle_ctr);
$display("State of DUT");
@@ -166,7 +161,7 @@ module tb_csprng_fifo();
//
// Dump the state of the fifo when needed.
//----------------------------------------------------------------
- task dump_fifo();
+ task dump_fifo;
begin
$display("contents of the fifo");
$display("--------------------");
@@ -181,28 +176,11 @@ module tb_csprng_fifo();
//----------------------------------------------------------------
- // gen_csprng_data
- //
- // Generate test data with distinct patterns as requested
- // by the dut.
- //----------------------------------------------------------------
-// always @ (posedge tb_more_data)
-// begin
-// for (i = 0 ; i < 16 ; i = i + 1)
-// tb_csprng_data[i * 32 +: 32] = tb_csprng_data[i * 32 +: 32] + 32'h10101010;
-//
-// tb_csprng_data_valid = 1'b1;
-// #(2 * CLK_PERIOD);
-// tb_csprng_data_valid = 1'b0;
-// end
-
-
- //----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
- task reset_dut();
+ task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
@@ -219,7 +197,7 @@ module tb_csprng_fifo();
//
// Display the accumulated test results.
//----------------------------------------------------------------
- task display_test_results();
+ task display_test_results;
begin
if (error_ctr == 0)
begin
@@ -240,7 +218,7 @@ module tb_csprng_fifo();
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
- task init_sim();
+ task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
@@ -269,7 +247,7 @@ module tb_csprng_fifo();
//
// Wait for the DUT to signal that it wants more data.
//----------------------------------------------------------------
- task wait_more_data();
+ task wait_more_data;
begin
while (!tb_more_data)
#(CLK_PERIOD);
@@ -341,7 +319,7 @@ module tb_csprng_fifo();
//
// read a 32 bit data word from the fifo.
//----------------------------------------------------------------
- task read_w32();
+ task read_w32;
begin
$display("*** Reading from the fifo: 0x%08x", tb_rnd_data);
tb_rnd_ack = 1;
@@ -359,7 +337,7 @@ module tb_csprng_fifo();
// extracts 32-bit words and checks that we get the correct
// words all the time.
//----------------------------------------------------------------
- task fifo_test();
+ task fifo_test;
reg [7 : 0] i;
reg [7 : 0] j;