diff options
Diffstat (limited to 'src/rtl')
| -rw-r--r-- | src/rtl/trng_csprng.v | 16 | ||||
| -rw-r--r-- | src/rtl/trng_csprng_fifo.v | 14 |
2 files changed, 15 insertions, 15 deletions
diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v index c682f27..85039ad 100644 --- a/src/rtl/trng_csprng.v +++ b/src/rtl/trng_csprng.v @@ -277,17 +277,17 @@ module trng_csprng( // All registers are positive edge triggered with synchronous // active low reset. All registers have write enable. //---------------------------------------------------------------- - always @ (posedge clk or negedge reset_n) + always @ (posedge clk) begin if (!reset_n) begin - cipher_key_reg <= {8{32'h00000000}}; - cipher_iv_reg <= {2{32'h00000000}}; - cipher_ctr_reg <= {2{32'h00000000}}; - cipher_block_reg <= {16{32'h00000000}}; - block_ctr_reg <= {2{32'h00000000}}; - block_stat_ctr_reg <= {2{32'h00000000}}; - reseed_stat_ctr_reg <= 32'h00000000; + cipher_key_reg <= {256'h0}; + cipher_iv_reg <= {64'h0}; + cipher_ctr_reg <= {64'h0}; + cipher_block_reg <= {512'h0}; + block_ctr_reg <= {64'h00}; + block_stat_ctr_reg <= {64'h0}; + reseed_stat_ctr_reg <= 32'h0; more_seed_reg <= 0; seed_ack_reg <= 0; ready_reg <= 0; diff --git a/src/rtl/trng_csprng_fifo.v b/src/rtl/trng_csprng_fifo.v index db0a1be..a58af0a 100644 --- a/src/rtl/trng_csprng_fifo.v +++ b/src/rtl/trng_csprng_fifo.v @@ -57,7 +57,7 @@ module trng_csprng_fifo( // Internal constant and parameter definitions. //---------------------------------------------------------------- localparam FIFO_ADDR_BITS = 2; - localparam FIFO_ADDR_MAX = (2**FIFO_ADDR_BITS) - 1; + localparam FIFO_ADDR_MAX = (2 ** FIFO_ADDR_BITS) - 1; localparam FIFO_MAX = (2 ** FIFO_ADDR_BITS); localparam WR_IDLE = 0; @@ -141,19 +141,19 @@ module trng_csprng_fifo( // // Register update. All registers have asynchronous reset. //---------------------------------------------------------------- - always @ (posedge clk or negedge reset_n) + always @ (posedge clk) begin if (!reset_n) begin - fifo_mem[00] <= {16{32'h00000000}}; - fifo_mem[01] <= {16{32'h00000000}}; - fifo_mem[02] <= {16{32'h00000000}}; - fifo_mem[03] <= {16{32'h00000000}}; + fifo_mem[00] <= {512'h0}; + fifo_mem[01] <= {512'h0}; + fifo_mem[02] <= {512'h0}; + fifo_mem[03] <= {512'h0}; mux_data_ptr_reg <= 4'h0; rd_ptr_reg <= {(FIFO_ADDR_BITS){1'b0}}; wr_ptr_reg <= {(FIFO_ADDR_BITS){1'b0}}; fifo_ctr_reg <= {FIFO_ADDR_BITS{1'b0}}; - rnd_data_reg <= 32'h00000000; + rnd_data_reg <= 32'h0; rnd_syn_reg <= 0; more_data_reg <= 0; wr_ctrl_reg <= WR_IDLE; |