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-rw-r--r--src/rtl/trng.v115
1 files changed, 47 insertions, 68 deletions
diff --git a/src/rtl/trng.v b/src/rtl/trng.v
index 06af515..c74f8b1 100644
--- a/src/rtl/trng.v
+++ b/src/rtl/trng.v
@@ -330,6 +330,44 @@ module trng(
//----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ begin
+ discard_reg <= 0;
+ test_mode_reg <= 0;
+ debug_mux_reg <= DEBUG_CSPRNG;
+ debug_delay_reg <= DEFAULT_DEBUG_DELAY;
+ debug_delay_ctr_reg <= 32'h00000000;
+ debug_out_reg <= 8'h00;
+ end
+ else
+ begin
+ discard_reg <= discard_new;
+ debug_delay_ctr_reg <= debug_delay_ctr_new;
+
+ if (debug_out_we)
+ debug_out_reg <= tmp_debug;
+
+ if (test_mode_we)
+ test_mode_reg <= test_mode_new;
+
+ if (debug_mux_we)
+ debug_mux_reg <= debug_mux_new;
+
+ if (debug_delay_we)
+ debug_delay_reg <= debug_delay_new;
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
// core_mux
//
// This is a simple decoder that looks at the top 4 bits of
@@ -380,44 +418,6 @@ module trng(
//----------------------------------------------------------------
- // reg_update
- //
- // Update functionality for all registers in the core.
- // All registers are positive edge triggered with asynchronous
- // active low reset.
- //----------------------------------------------------------------
- always @ (posedge clk or negedge reset_n)
- begin
- if (!reset_n)
- begin
- discard_reg <= 0;
- test_mode_reg <= 0;
- debug_mux_reg <= DEBUG_CSPRNG;
- debug_delay_reg <= DEFAULT_DEBUG_DELAY;
- debug_delay_ctr_reg <= 32'h00000000;
- debug_out_reg <= 8'h00;
- end
- else
- begin
- discard_reg <= discard_new;
- debug_delay_ctr_reg <= debug_delay_ctr_new;
-
- if (debug_out_we)
- debug_out_reg <= tmp_debug;
-
- if (test_mode_we)
- test_mode_reg <= test_mode_new;
-
- if (debug_mux_we)
- debug_mux_reg <= debug_mux_new;
-
- if (debug_delay_we)
- debug_delay_reg <= debug_delay_new;
- end
- end // reg_update
-
-
- //----------------------------------------------------------------
// debug_update_logic
//
// Debug update counter and update logic.
@@ -506,9 +506,7 @@ module trng(
begin
if (trng_api_we)
begin
- // Write operations.
case (api_address)
- // Write operations.
ADDR_TRNG_CTRL:
begin
discard_new = write_data[TRNG_CTRL_DISCARD_BIT];
@@ -529,61 +527,42 @@ module trng(
end
default:
- begin
- trng_api_error = 1;
- end
+ trng_api_error = 1;
endcase // case (address)
end // if (we)
else
begin
- // Read operations.
case (api_address)
- // Read operations.
ADDR_NAME0:
- begin
- trng_api_read_data = TRNG_NAME0;
- end
+ trng_api_read_data = TRNG_NAME0;
ADDR_NAME1:
- begin
- trng_api_read_data = TRNG_NAME1;
- end
+ trng_api_read_data = TRNG_NAME1;
ADDR_VERSION:
- begin
- trng_api_read_data = TRNG_VERSION;
- end
+ trng_api_read_data = TRNG_VERSION;
ADDR_TRNG_CTRL:
- begin
- trng_api_read_data = {30'h0000000, test_mode_reg, discard_reg};
- end
+ trng_api_read_data = {30'h0000000, test_mode_reg, discard_reg};
ADDR_TRNG_STATUS:
begin
-
+ // No error caused by reading status.
end
ADDR_DEBUG_CTRL:
- begin
- trng_api_read_data = {29'h0000000, debug_mux_new};
- end
+ trng_api_read_data = {29'h0000000, debug_mux_new};
ADDR_DEBUG_DELAY:
- begin
- trng_api_read_data = debug_delay_reg;
- end
+ trng_api_read_data = debug_delay_reg;
default:
- begin
- trng_api_error = 1;
- end
+ trng_api_error = 1;
endcase // case (address)
end
end
end // trng_api_logic
-
endmodule // trng
//======================================================================