diff options
Diffstat (limited to 'src/rtl/trng.v')
| -rw-r--r-- | src/rtl/trng.v | 121 |
1 files changed, 51 insertions, 70 deletions
diff --git a/src/rtl/trng.v b/src/rtl/trng.v index 9e8bf69..7a15e7e 100644 --- a/src/rtl/trng.v +++ b/src/rtl/trng.v @@ -76,17 +76,18 @@ module trng( localparam ADDR_NAME1 = 8'h01; localparam ADDR_VERSION = 8'h02; - localparam ADDR_TRNG_CTRL = 8'h10; + localparam ADDR_TRNG_CTRL = 8'h08; localparam TRNG_CTRL_DISCARD_BIT = 0; localparam TRNG_CTRL_TEST_MODE_BIT = 1; - localparam ADDR_TRNG_STATUS = 8'h11; + localparam ADDR_TRNG_STATUS = 8'h09; + localparam ADDR_DEBUG_CTRL = 8'h12; localparam ADDR_DEBUG_DELAY = 8'h13; localparam TRNG_NAME0 = 32'h74726e67; // "trng" localparam TRNG_NAME1 = 32'h20202020; // " " - localparam TRNG_VERSION = 32'h302e3530; // "0.50" + localparam TRNG_VERSION = 32'h302e3531; // "0.51" // 20x/s @ 50 MHz. localparam DEFAULT_DEBUG_DELAY = 32'h002625a0; @@ -329,6 +330,44 @@ module trng( //---------------------------------------------------------------- + // reg_update + // + // Update functionality for all registers in the core. + // All registers are positive edge triggered with asynchronous + // active low reset. + //---------------------------------------------------------------- + always @ (posedge clk or negedge reset_n) + begin + if (!reset_n) + begin + discard_reg <= 0; + test_mode_reg <= 0; + debug_mux_reg <= DEBUG_CSPRNG; + debug_delay_reg <= DEFAULT_DEBUG_DELAY; + debug_delay_ctr_reg <= 32'h00000000; + debug_out_reg <= 8'h00; + end + else + begin + discard_reg <= discard_new; + debug_delay_ctr_reg <= debug_delay_ctr_new; + + if (debug_out_we) + debug_out_reg <= tmp_debug; + + if (test_mode_we) + test_mode_reg <= test_mode_new; + + if (debug_mux_we) + debug_mux_reg <= debug_mux_new; + + if (debug_delay_we) + debug_delay_reg <= debug_delay_new; + end + end // reg_update + + + //---------------------------------------------------------------- // core_mux // // This is a simple decoder that looks at the top 4 bits of @@ -379,44 +418,6 @@ module trng( //---------------------------------------------------------------- - // reg_update - // - // Update functionality for all registers in the core. - // All registers are positive edge triggered with asynchronous - // active low reset. - //---------------------------------------------------------------- - always @ (posedge clk or negedge reset_n) - begin - if (!reset_n) - begin - discard_reg <= 0; - test_mode_reg <= 0; - debug_mux_reg <= DEBUG_CSPRNG; - debug_delay_reg <= DEFAULT_DEBUG_DELAY; - debug_delay_ctr_reg <= 32'h00000000; - debug_out_reg <= 8'h00; - end - else - begin - discard_reg <= discard_new; - debug_delay_ctr_reg <= debug_delay_ctr_new; - - if (debug_out_we) - debug_out_reg <= tmp_debug; - - if (test_mode_we) - test_mode_reg <= test_mode_new; - - if (debug_mux_we) - debug_mux_reg <= debug_mux_new; - - if (debug_delay_we) - debug_delay_reg <= debug_delay_new; - end - end // reg_update - - - //---------------------------------------------------------------- // debug_update_logic // // Debug update counter and update logic. @@ -505,9 +506,7 @@ module trng( begin if (trng_api_we) begin - // Write operations. case (api_address) - // Write operations. ADDR_TRNG_CTRL: begin discard_new = write_data[TRNG_CTRL_DISCARD_BIT]; @@ -528,60 +527,42 @@ module trng( end default: - begin - trng_api_error = 1; - end + trng_api_error = 1; endcase // case (address) end // if (we) else begin - // Read operations. case (api_address) - // Read operations. ADDR_NAME0: - begin - trng_api_read_data = TRNG_NAME0; - end + trng_api_read_data = TRNG_NAME0; ADDR_NAME1: - begin - trng_api_read_data = TRNG_NAME1; - end + trng_api_read_data = TRNG_NAME1; ADDR_VERSION: - begin - trng_api_read_data = TRNG_VERSION; - end + trng_api_read_data = TRNG_VERSION; ADDR_TRNG_CTRL: - begin - end + trng_api_read_data = {30'h0000000, test_mode_reg, discard_reg}; ADDR_TRNG_STATUS: begin - + // No error caused by reading status. end ADDR_DEBUG_CTRL: - begin - trng_api_read_data = {29'h0000000, debug_mux_new}; - end + trng_api_read_data = {29'h0000000, debug_mux_new}; ADDR_DEBUG_DELAY: - begin - trng_api_read_data = debug_delay_reg; - end + trng_api_read_data = debug_delay_reg; default: - begin - trng_api_error = 1; - end + trng_api_error = 1; endcase // case (address) end end end // trng_api_logic - endmodule // trng //====================================================================== |