diff options
| -rw-r--r-- | src/rtl/trng_csprng_fifo.v | 115 |
1 files changed, 57 insertions, 58 deletions
diff --git a/src/rtl/trng_csprng_fifo.v b/src/rtl/trng_csprng_fifo.v index 19539d9..adbc83a 100644 --- a/src/rtl/trng_csprng_fifo.v +++ b/src/rtl/trng_csprng_fifo.v @@ -75,49 +75,49 @@ module trng_csprng_fifo( reg [511 : 0] fifo_mem [0 : FIFO_MAX]; reg fifo_mem_we; - reg [3 : 0] mux_data_ptr_reg; - reg [3 : 0] mux_data_ptr_new; - reg mux_data_ptr_inc; - reg mux_data_ptr_rst; - reg mux_data_ptr_we; - - reg [1 : 0] wr_ptr_reg; - reg [1 : 0] wr_ptr_new; - reg wr_ptr_inc; - reg wr_ptr_rst; - reg wr_ptr_we; - - reg [1 : 0] rd_ptr_reg; - reg [1 : 0] rd_ptr_new; - reg rd_ptr_inc; - reg rd_ptr_rst; - reg rd_ptr_we; - - reg [31 : 0] rnd_data_reg; - - reg rnd_syn_reg; - reg rnd_syn_new; - reg rnd_syn_we; - - reg [FIFO_ADDR_MAX : 0] rd_ctrl_reg; - reg [FIFO_ADDR_MAX : 0] rd_ctrl_new; - reg rd_ctrl_we; - - reg [FIFO_ADDR_MAX : 0] wr_ctrl_reg; - reg [FIFO_ADDR_MAX : 0] wr_ctrl_new; - reg wr_ctrl_we; - - reg [2 : 0] fifo_ctr_reg; - reg [2 : 0] fifo_ctr_new; - reg fifo_ctr_inc; - reg fifo_ctr_dec; - reg fifo_ctr_rst; - reg fifo_ctr_we; - reg fifo_empty; - reg fifo_full; - - reg more_data_reg; - reg more_data_new; + reg [3 : 0] mux_data_ptr_reg; + reg [3 : 0] mux_data_ptr_new; + reg mux_data_ptr_inc; + reg mux_data_ptr_rst; + reg mux_data_ptr_we; + + reg [FIFO_ADDR_MAX : 0] rd_ptr_reg; + reg [FIFO_ADDR_MAX : 0] rd_ptr_new; + reg rd_ptr_inc; + reg rd_ptr_rst; + reg rd_ptr_we; + + reg [FIFO_ADDR_MAX : 0] wr_ptr_reg; + reg [FIFO_ADDR_MAX : 0] wr_ptr_new; + reg wr_ptr_inc; + reg wr_ptr_rst; + reg wr_ptr_we; + + reg [FIFO_ADDR_MAX : 0] fifo_ctr_reg; + reg [FIFO_ADDR_MAX : 0] fifo_ctr_new; + reg fifo_ctr_inc; + reg fifo_ctr_dec; + reg fifo_ctr_rst; + reg fifo_ctr_we; + reg fifo_empty; + reg fifo_full; + + reg [31 : 0] rnd_data_reg; + + reg rnd_syn_reg; + reg rnd_syn_new; + reg rnd_syn_we; + + reg [2 : 0] rd_ctrl_reg; + reg [2 : 0] rd_ctrl_new; + reg rd_ctrl_we; + + reg [2 : 0] wr_ctrl_reg; + reg [2 : 0] wr_ctrl_new; + reg wr_ctrl_we; + + reg more_data_reg; + reg more_data_new; //---------------------------------------------------------------- @@ -150,7 +150,7 @@ module trng_csprng_fifo( mux_data_ptr_reg <= 4'h0; rd_ptr_reg <= {FIFO_ADDR_BITS{1'b0}}; wr_ptr_reg <= {FIFO_ADDR_BITS{1'b0}}; - fifo_ctr_reg <= 3'h0; + fifo_ctr_reg <= {FIFO_ADDR_BITS{1'b0}}; rnd_data_reg <= 32'h00000000; rnd_syn_reg <= 0; more_data_reg <= 0; @@ -281,7 +281,7 @@ module trng_csprng_fifo( if (rd_ptr_inc) begin fifo_ctr_dec = 1; - if (rd_ptr_reg == FIFO_ADDR_MAX) + if (rd_ptr_reg == FIFO_MAX) rd_ptr_we = 1; else begin @@ -307,7 +307,7 @@ module trng_csprng_fifo( if (wr_ptr_inc) begin - if (wr_ptr_reg == FIFO_ADDR_MAX) + if (wr_ptr_reg == FIFO_MAX) wr_ptr_we = 1; else begin @@ -321,18 +321,20 @@ module trng_csprng_fifo( //---------------------------------------------------------------- // fifo_ctr // - // fifo counter tracks the number of elements and also signals - // the csprng when more data is needed as well as applications - // that random numbers are available. + // fifo counter tracks the number of 512 bit elements currently + // in the fifp. The counter also signals the csprng when more + // data is needed. The fifo also signals applications when + // random numbers are available, that is there is at least + // one elemnt in the fifo with 32-bit words not yet used. //---------------------------------------------------------------- always @* begin : fifo_ctr - fifo_ctr_new = 3'h0; + fifo_ctr_new = {FIFO_ADDR_BITS{1'b0}}; fifo_ctr_we = 0; fifo_empty = 0; fifo_full = 0; - if (fifo_ctr_reg == 3'h0) + if (fifo_ctr_reg == 0) begin fifo_empty = 1; end @@ -342,23 +344,20 @@ module trng_csprng_fifo( fifo_full = 1; end + if (fifo_ctr_rst) + fifo_ctr_we = 1; + if ((fifo_ctr_inc) && (fifo_ctr_reg < FIFO_MAX)) begin fifo_ctr_new = fifo_ctr_reg + 1'b1; fifo_ctr_we = 1; end - if ((fifo_ctr_dec) && (fifo_ctr_reg > 3'h0)) + if ((fifo_ctr_dec) && (fifo_ctr_reg > 0)) begin fifo_ctr_new = fifo_ctr_reg - 1'b1; fifo_ctr_we = 1; end - - if (fifo_ctr_rst) - begin - fifo_ctr_new = 3'h0; - fifo_ctr_we = 1; - end end // fifo_ctr |