diff options
-rw-r--r-- | src/rtl/trng.v | 80 | ||||
-rw-r--r-- | src/rtl/trng_csprng.v | 36 | ||||
-rw-r--r-- | src/rtl/trng_mixer.v | 157 |
3 files changed, 226 insertions, 47 deletions
diff --git a/src/rtl/trng.v b/src/rtl/trng.v index 7d0e45d..e2b9212 100644 --- a/src/rtl/trng.v +++ b/src/rtl/trng.v @@ -82,11 +82,15 @@ module trng( parameter ADDR_TRNG_STATUS = 8'h11; parameter ADDR_DEBUG_CTRL = 8'h12; + parameter ADDR_DEBUG_DELAY = 8'h13; parameter TRNG_NAME0 = 32'h74726e67; // "trng" parameter TRNG_NAME1 = 32'h20202020; // " " parameter TRNG_VERSION = 32'h302e3031; // "0.01" + // 20x/s @ 50 MHz. + parameter DEFAULT_DEBUG_DELAY = 32'h002625a0; + //---------------------------------------------------------------- // Registers including update variables and write enable. @@ -98,10 +102,21 @@ module trng( reg test_mode_new; reg test_mode_we; + reg [7 : 0] debug_out_reg; + reg debug_out_we; + reg [2 : 0] debug_mux_reg; reg [2 : 0] debug_mux_new; reg [2 : 0] debug_mux_we; + reg [31 : 0] debug_delay_ctr_reg; + reg [31 : 0] debug_delay_ctr_new; + reg debug_delay_ctr_we; + + reg [31 : 0] debug_delay_reg; + reg [31 : 0] debug_delay_new; + reg debug_delay_we; + //---------------------------------------------------------------- // Wires. @@ -119,6 +134,7 @@ module trng( reg mixer_api_we; wire [31 : 0] mixer_api_read_data; wire mixer_api_error; + wire mixer_security_error; wire [7 : 0] mixer_debug; reg mixer_debug_update; @@ -130,6 +146,7 @@ module trng( wire csprng_api_error; wire [7 : 0] csprng_debug; reg csprng_debug_update; + wire csprng_security_error; wire entropy0_entropy_enabled; wire [31 : 0] entropy0_entropy_data; @@ -174,7 +191,7 @@ module trng( assign read_data = tmp_read_data; assign error = tmp_error; assign security_error = entropy1_security_error | entropy2_security_error; - assign debug = tmp_debug; + assign debug = debug_out_reg; // Patches to get our first version to work. assign entropy0_entropy_enabled = 0; @@ -198,6 +215,7 @@ module trng( .discard(discard_reg), .test_mode(test_mode_reg), + .security_error(mixer_security_error), .more_seed(csprng_more_seed), @@ -237,6 +255,7 @@ module trng( .discard(discard_reg), .test_mode(test_mode_reg), + .security_error(csprng_security_error), .more_seed(csprng_more_seed), @@ -310,13 +329,22 @@ module trng( begin if (!reset_n) begin - discard_reg <= 0; - test_mode_reg <= 0; - debug_mux_reg <= DEBUG_ENTROPY1; + discard_reg <= 0; + test_mode_reg <= 0; + debug_mux_reg <= DEBUG_CSPRNG; + debug_delay_reg <= DEFAULT_DEBUG_DELAY; + debug_delay_ctr_reg <= 32'h00000000; + debug_out_reg <= 8'h00; end else begin - discard_reg <= discard_new; + discard_reg <= discard_new; + debug_delay_ctr_reg <= debug_delay_ctr_new; + + if (debug_out_we) + begin + debug_out_reg <= tmp_debug; + end if (test_mode_we) begin @@ -327,12 +355,40 @@ module trng( begin debug_mux_reg <= debug_mux_new; end + + if (debug_delay_we) + begin + debug_delay_reg <= debug_delay_new; + end end end // reg_update //---------------------------------------------------------------- + // debug_update_logic + // + // Debug update counter and update logic. + //---------------------------------------------------------------- + always @* + begin : debug_update_logic + if (debug_delay_ctr_reg == debug_delay_reg) + begin + debug_out_we = 1; + debug_delay_ctr_new = 32'h00000000; + end + else + begin + debug_out_we = 0; + debug_delay_ctr_new = debug_delay_ctr_reg + 1'b1; + end + end // debug_update + + + //---------------------------------------------------------------- // debug_mux + // + // Select which of the sub modules that are connected to + // the debug port. //---------------------------------------------------------------- always @* begin : debug_mux @@ -373,7 +429,6 @@ module trng( end endcase // case (debug_mux_reg) - end // debug_mux @@ -467,6 +522,8 @@ module trng( test_mode_we = 0; debug_mux_new = 3'h0; debug_mux_we = 0; + debug_delay_new = 32'h00000000; + debug_delay_we = 0; trng_api_read_data = 32'h00000000; trng_api_error = 0; @@ -490,6 +547,12 @@ module trng( debug_mux_we = 1; end + ADDR_DEBUG_DELAY: + begin + debug_delay_new = write_data; + debug_delay_we = 1; + end + default: begin trng_api_error = 1; @@ -531,6 +594,11 @@ module trng( trng_api_read_data = debug_mux_new; end + ADDR_DEBUG_DELAY: + begin + trng_api_read_data = debug_delay_reg; + end + default: begin trng_api_error = 1; diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v index 83c383f..c4576e8 100644 --- a/src/rtl/trng_csprng.v +++ b/src/rtl/trng_csprng.v @@ -65,6 +65,19 @@ module trng_csprng( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- + parameter ADDR_CTRL = 8'h10; + parameter CTRL_ENABLE_BIT = 0; + parameter CTRL_SEED_BIT = 1; + + parameter ADDR_STATUS = 8'h11; + parameter STATUS_RND_VALID_BIT = 0; + + parameter ADDR_RND_DATA = 8'h20; + + parameter ADDR_NUM_ROUNDS = 8'h40; + parameter ADDR_NUM_BLOCKS_LOW = 8'h41; + parameter ADDR_NUM_BLOCKS_HIGH = 8'h42; + parameter CIPHER_KEYLEN256 = 1'b1; // 256 bit key. parameter CIPHER_MAX_BLOCKS = 64'h1000000000000000; @@ -82,19 +95,6 @@ module trng_csprng( parameter DEFAULT_NUM_ROUNDS = 5'h18; parameter DEFAULT_NUM_BLOCKS = 64'h1000000000000000; - parameter ADDR_CTRL = 8'h10; - parameter CTRL_ENABLE_BIT = 0; - parameter CTRL_SEED_BIT = 1; - - parameter ADDR_STATUS = 8'h11; - parameter STATUS_RND_VALID_BIT = 0; - - parameter ADDR_RND_DATA = 8'h20; - - parameter ADDR_NUM_ROUNDS = 8'h40; - parameter ADDR_NUM_BLOCK_LOW = 8'h41; - parameter ADDR_NUM_BLOCK_HIGH = 8'h42; - //---------------------------------------------------------------- // Registers including update variables and write enable. @@ -253,7 +253,7 @@ module trng_csprng( more_seed_reg <= 0; seed_ack_reg <= 0; ready_reg <= 0; - enable_reg <= 0; + enable_reg <= 1; seed_reg <= 0; num_rounds_reg <= DEFAULT_NUM_ROUNDS; num_blocks_low_reg <= DEFAULT_NUM_BLOCKS[31 : 0]; @@ -366,13 +366,13 @@ module trng_csprng( num_rounds_we = 1; end - ADDR_NUM_BLOCK_LOW: + ADDR_NUM_BLOCKS_LOW: begin num_blocks_low_new = write_data; num_blocks_low_we = 1; end - ADDR_NUM_BLOCK_HIGH: + ADDR_NUM_BLOCKS_HIGH: begin num_blocks_high_new = write_data; num_blocks_high_we = 1; @@ -411,12 +411,12 @@ module trng_csprng( tmp_read_data = {27'h0000000, num_rounds_reg}; end - ADDR_NUM_BLOCK_LOW: + ADDR_NUM_BLOCKS_LOW: begin tmp_read_data = num_blocks_low_reg; end - ADDR_NUM_BLOCK_HIGH: + ADDR_NUM_BLOCKS_HIGH: begin tmp_read_data = num_blocks_high_reg; end diff --git a/src/rtl/trng_mixer.v b/src/rtl/trng_mixer.v index d11050c..821601b 100644 --- a/src/rtl/trng_mixer.v +++ b/src/rtl/trng_mixer.v @@ -49,6 +49,7 @@ module trng_mixer( input wire discard, input wire test_mode, + output wire security_error, input wire more_seed, @@ -81,13 +82,6 @@ module trng_mixer( //---------------------------------------------------------------- parameter MODE_SHA_512 = 2'h3; - parameter CTRL_IDLE = 4'h0; - parameter CTRL_COLLECT = 4'h1; - parameter CTRL_MIX = 4'h2; - parameter CTRL_SYN = 4'h3; - parameter CTRL_ACK = 4'h4; - parameter CTRL_NEXT = 4'h5; - parameter ENTROPY_IDLE = 4'h0; parameter ENTROPY_SRC0 = 4'h1; parameter ENTROPY_SRC0_ACK = 4'h2; @@ -96,11 +90,20 @@ module trng_mixer( parameter ENTROPY_SRC2 = 4'h5; parameter ENTROPY_SRC2_ACK = 4'h6; + parameter CTRL_IDLE = 4'h0; + parameter CTRL_COLLECT = 4'h1; + parameter CTRL_MIX = 4'h2; + parameter CTRL_SYN = 4'h3; + parameter CTRL_ACK = 4'h4; + parameter CTRL_NEXT = 4'h5; + parameter ADDR_MIXER_CTRL = 8'h10; parameter MIXER_CTRL_ENABLE_BIT = 0; parameter MIXER_CTRL_RESTART_BIT = 1; - parameter ADDR_MIXER_STATUS = 8'h11; + parameter ADDR_MIXER_TIMEOUT = 8'h20; + + parameter DEFAULT_ENTROPY_TIMEOUT = 24'h800000; //---------------------------------------------------------------- @@ -181,6 +184,17 @@ module trng_mixer( reg [3 : 0] entropy_collect_ctrl_new; reg entropy_collect_ctrl_we; + reg [23 : 0] entropy_timeout_ctr_reg; + reg [23 : 0] entropy_timeout_ctr_new; + reg entropy_timeout_ctr_inc; + reg entropy_timeout_ctr_rst; + reg entropy_timeout_ctr_we; + reg entropy_timeout; + + reg [23 : 0] entropy_timeout_reg; + reg [23 : 0] entropy_timeout_new; + reg entropy_timeout_we; + reg [3 : 0] mixer_ctrl_reg; reg [3 : 0] mixer_ctrl_new; reg mixer_ctrl_we; @@ -228,8 +242,9 @@ module trng_mixer( //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- - assign read_data = tmp_read_data; - assign error = tmp_error; + assign read_data = tmp_read_data; + assign error = tmp_error; + assign security_error = 0; assign seed_syn = seed_syn_reg; assign seed_data = hash_digest; @@ -317,8 +332,10 @@ module trng_mixer( init_done_reg <= 0; word_ctr_reg <= 5'h00; seed_syn_reg <= 0; - enable_reg <= 0; + enable_reg <= 1; restart_reg <= 0; + entropy_timeout_reg <= DEFAULT_ENTROPY_TIMEOUT; + entropy_timeout_ctr_reg <= 24'h000000; entropy_collect_ctrl_reg <= CTRL_IDLE; mixer_ctrl_reg <= CTRL_IDLE; end @@ -515,6 +532,16 @@ module trng_mixer( begin mixer_ctrl_reg <= mixer_ctrl_new; end + + if (entropy_timeout_we) + begin + entropy_timeout_reg <= entropy_timeout_new; + end + + if (entropy_timeout_ctr_we) + begin + entropy_timeout_ctr_reg <= entropy_timeout_ctr_new; + end end end // reg_update @@ -524,12 +551,14 @@ module trng_mixer( //---------------------------------------------------------------- always @* begin : mixer_api_logic - enable_new = 0; - enable_we = 0; - restart_reg = 0; - restart_new = 0; - tmp_read_data = 32'h00000000; - tmp_error = 0; + enable_new = 0; + enable_we = 0; + restart_reg = 0; + restart_new = 0; + entropy_timeout_new = 24'h000000; + entropy_timeout_we = 0; + tmp_read_data = 32'h00000000; + tmp_error = 0; if (cs) begin @@ -545,6 +574,12 @@ module trng_mixer( restart_new = write_data[MIXER_CTRL_RESTART_BIT]; end + ADDR_MIXER_TIMEOUT: + begin + entropy_timeout_new = write_data[23 : 0]; + entropy_timeout_we = 1; + end + default: begin tmp_error = 1; @@ -559,12 +594,17 @@ module trng_mixer( // Read operations. ADDR_MIXER_CTRL: begin - tmp_read_data = {30'h00000000, restart_reg, enable_reg}; + tmp_read_data = {restart_reg, enable_reg}; end ADDR_MIXER_STATUS: begin + tmp_read_data = 32'h00000000; + end + ADDR_MIXER_TIMEOUT: + begin + tmp_read_data = entropy_timeout_reg; end default: @@ -594,6 +634,8 @@ module trng_mixer( update_block = 0; block_done = 0; muxed_entropy = 32'h00000000; + entropy_timeout_ctr_inc = 0; + entropy_timeout_ctr_rst = 0; entropy_collect_ctrl_new = ENTROPY_IDLE; entropy_collect_ctrl_we = 0; @@ -603,6 +645,7 @@ module trng_mixer( if (collect_block) begin word_ctr_rst = 1; + entropy_timeout_ctr_rst = 1; entropy_collect_ctrl_new = ENTROPY_SRC0; entropy_collect_ctrl_we = 1; end @@ -627,9 +670,21 @@ module trng_mixer( entropy_collect_ctrl_new = ENTROPY_SRC0_ACK; entropy_collect_ctrl_we = 1; end + else + if (entropy_timeout) + begin + entropy_timeout_ctr_rst = 1; + entropy_collect_ctrl_new = ENTROPY_SRC1; + entropy_collect_ctrl_we = 1; + end + else + begin + entropy_timeout_ctr_inc = 1; + end end else begin + entropy_timeout_ctr_rst = 1; entropy_collect_ctrl_new = ENTROPY_SRC1; entropy_collect_ctrl_we = 1; end @@ -682,6 +737,17 @@ module trng_mixer( entropy_collect_ctrl_new = ENTROPY_SRC1_ACK; entropy_collect_ctrl_we = 1; end + else + if (entropy_timeout) + begin + entropy_timeout_ctr_rst = 1; + entropy_collect_ctrl_new = ENTROPY_SRC2; + entropy_collect_ctrl_we = 1; + end + else + begin + entropy_timeout_ctr_inc = 1; + end end else begin @@ -736,6 +802,17 @@ module trng_mixer( entropy_collect_ctrl_new = ENTROPY_SRC2_ACK; entropy_collect_ctrl_we = 1; end + else + if (entropy_timeout) + begin + entropy_timeout_ctr_rst = 1; + entropy_collect_ctrl_new = ENTROPY_SRC0; + entropy_collect_ctrl_we = 1; + end + else + begin + entropy_timeout_ctr_inc = 1; + end end else begin @@ -854,6 +931,40 @@ module trng_mixer( //---------------------------------------------------------------- + // entropy_timeout_logic + // + // Logic that updates the entropy timeout counter and signals + // when the wait for antropy from a provider has exceeded + // acceptable time. + //---------------------------------------------------------------- + always @* + begin : entropy_timeout_logic + entropy_timeout_ctr_new = 24'h000000; + entropy_timeout_ctr_we = 0; + entropy_timeout = 0; + + if (entropy_timeout_ctr_reg == entropy_timeout_reg) + begin + entropy_timeout = 1; + entropy_timeout_ctr_new = 24'h000000; + entropy_timeout_ctr_we = 1; + end + + if (entropy_timeout_ctr_rst) + begin + entropy_timeout_ctr_new = 24'h000000; + entropy_timeout_ctr_we = 1; + end + + if (entropy_timeout_ctr_inc) + begin + entropy_timeout_ctr_new = entropy_timeout_ctr_reg + 1'b1; + entropy_timeout_ctr_we = 1; + end + end + + + //---------------------------------------------------------------- // word_ctr //---------------------------------------------------------------- always @* @@ -907,7 +1018,7 @@ module trng_mixer( CTRL_COLLECT: begin - if ((!discard)) + if ((discard)) begin mixer_ctrl_new = CTRL_IDLE; mixer_ctrl_we = 1; @@ -924,7 +1035,7 @@ module trng_mixer( CTRL_MIX: begin - if ((!discard)) + if ((discard)) begin mixer_ctrl_new = CTRL_IDLE; mixer_ctrl_we = 1; @@ -946,7 +1057,7 @@ module trng_mixer( CTRL_SYN: begin - if ((!discard)) + if ((discard)) begin mixer_ctrl_new = CTRL_IDLE; mixer_ctrl_we = 1; @@ -963,7 +1074,7 @@ module trng_mixer( CTRL_ACK: begin - if ((!discard)) + if ((discard)) begin mixer_ctrl_new = CTRL_IDLE; mixer_ctrl_we = 1; @@ -979,7 +1090,7 @@ module trng_mixer( CTRL_NEXT: begin - if ((!discard)) + if ((discard)) begin mixer_ctrl_new = CTRL_IDLE; mixer_ctrl_we = 1; |