Cleanup: Merged separate clocked processes. Fixed incorrect bit widths. Changed to localparams. Changed api data read reg to real hold register.

1 files changed, 68 insertions, 73 deletions

diff --git a/src/rtl/trng.v b/src/rtl/trng.v
index 0e0286e..2ef30fb 100644
--- a/src/rtl/trng.v
+++ b/src/rtl/trng.v
@@ -60,36 +60,36 @@ module trng(
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
-  parameter TRNG_PREFIX             = 4'h0;
-  parameter ENTROPY1_PREFIX         = 4'h5;
-  parameter ENTROPY2_PREFIX         = 4'h6;
-  parameter MIXER_PREFIX            = 4'ha;
-  parameter CSPRNG_PREFIX           = 4'hb;
-
-  parameter DEBUG_ENTROPY0          = 3'h0;
-  parameter DEBUG_ENTROPY1          = 3'h1;
-  parameter DEBUG_ENTROPY2          = 3'h2;
-  parameter DEBUG_MIXER             = 3'h3;
-  parameter DEBUG_CSPRNG            = 3'h4;
-
-  parameter ADDR_NAME0              = 8'h00;
-  parameter ADDR_NAME1              = 8'h01;
-  parameter ADDR_VERSION            = 8'h02;
-
-  parameter ADDR_TRNG_CTRL          = 8'h10;
-  parameter TRNG_CTRL_DISCARD_BIT   = 0;
-  parameter TRNG_CTRL_TEST_MODE_BIT = 1;
-
-  parameter ADDR_TRNG_STATUS        = 8'h11;
-  parameter ADDR_DEBUG_CTRL         = 8'h12;
-  parameter ADDR_DEBUG_DELAY        = 8'h13;
-
-  parameter TRNG_NAME0              = 32'h74726e67; // "trng"
-  parameter TRNG_NAME1              = 32'h20202020; // "    "
-  parameter TRNG_VERSION            = 32'h302e3031; // "0.01"
+  localparam TRNG_PREFIX             = 4'h0;
+  localparam ENTROPY1_PREFIX         = 4'h5;
+  localparam ENTROPY2_PREFIX         = 4'h6;
+  localparam MIXER_PREFIX            = 4'ha;
+  localparam CSPRNG_PREFIX           = 4'hb;
+
+  localparam DEBUG_ENTROPY0          = 3'h0;
+  localparam DEBUG_ENTROPY1          = 3'h1;
+  localparam DEBUG_ENTROPY2          = 3'h2;
+  localparam DEBUG_MIXER             = 3'h3;
+  localparam DEBUG_CSPRNG            = 3'h4;
+
+  localparam ADDR_NAME0              = 8'h00;
+  localparam ADDR_NAME1              = 8'h01;
+  localparam ADDR_VERSION            = 8'h02;
+
+  localparam ADDR_TRNG_CTRL          = 8'h10;
+  localparam TRNG_CTRL_DISCARD_BIT   = 0;
+  localparam TRNG_CTRL_TEST_MODE_BIT = 1;
+
+  localparam ADDR_TRNG_STATUS        = 8'h11;
+  localparam ADDR_DEBUG_CTRL         = 8'h12;
+  localparam ADDR_DEBUG_DELAY        = 8'h13;
+
+  localparam TRNG_NAME0              = 32'h74726e67; // "trng"
+  localparam TRNG_NAME1              = 32'h20202020; // "    "
+  localparam TRNG_VERSION            = 32'h302e3031; // "0.01"
 
   // 20x/s @ 50 MHz.
-  parameter DEFAULT_DEBUG_DELAY     = 32'h002625a0;
+  localparam DEFAULT_DEBUG_DELAY     = 32'h002625a0;
 
 
   //----------------------------------------------------------------
@@ -123,8 +123,9 @@ module trng(
   //----------------------------------------------------------------
   wire           trng_api_cs = cs && (addr_core_num == TRNG_PREFIX);
   wire           trng_api_we = we;
-  reg [31 : 0]   trng_api_read_data;
   reg [31 : 0]   trng_api_read_data_reg;
+  reg [31 : 0]   trng_api_read_data_new;
+  reg [31 : 0]   trng_api_read_data;
   reg            trng_api_error;
 
   wire           mixer_more_seed;
@@ -200,11 +201,14 @@ module trng(
   assign entropy0_entropy_data    = 32'h00000000;
 
 
-   //----------------------------------------------------------------
-   // Address Decoder
-   //----------------------------------------------------------------
-   wire [ 5: 0]  addr_core_num   = address[11: 8];  // upper 4 bits specify core being addressed
-   wire [ 7: 0]  addr_core_reg   = address[7: 0];  // lower 8 bits specify register offset in core
+  //----------------------------------------------------------------
+  // Address Decoder
+  //----------------------------------------------------------------
+  // upper 4 bits specify core being addressed.
+  wire [3 : 0] addr_core_num = address[11 : 8];
+
+  // lower 8 bits specify register offset in core.
+  wire [7 : 0] addr_core_reg = address[7 : 0];
 
 
   //----------------------------------------------------------------
@@ -387,37 +391,33 @@ module trng(
     begin
       if (!reset_n)
         begin
-          discard_reg         <= 0;
-          test_mode_reg       <= 0;
-          debug_mux_reg       <= DEBUG_CSPRNG;
-          debug_delay_reg     <= DEFAULT_DEBUG_DELAY;
-          debug_delay_ctr_reg <= 32'h00000000;
-          debug_out_reg       <= 8'h00;
+          discard_reg            <= 0;
+          test_mode_reg          <= 0;
+          debug_mux_reg          <= DEBUG_CSPRNG;
+          debug_delay_reg        <= DEFAULT_DEBUG_DELAY;
+          debug_delay_ctr_reg    <= 32'h00000000;
+          debug_out_reg          <= 8'h00;
+          trng_api_read_data_reg <= 32'h00000000;
         end
       else
         begin
-          discard_reg         <= discard_new;
-          debug_delay_ctr_reg <= debug_delay_ctr_new;
+          discard_reg            <= discard_new;
+          debug_delay_ctr_reg    <= debug_delay_ctr_new;
+
+          if (trng_api_cs)
+            trng_api_read_data_reg <= trng_api_read_data_new;
 
           if (debug_out_we)
-            begin
-              debug_out_reg <= tmp_debug;
-            end
+            debug_out_reg <= tmp_debug;
 
           if (test_mode_we)
-            begin
-              test_mode_reg <= test_mode_new;
-            end
+            test_mode_reg <= test_mode_new;
 
           if (debug_mux_we)
-            begin
-              debug_mux_reg <= debug_mux_new;
-            end
+            debug_mux_reg <= debug_mux_new;
 
           if (debug_delay_we)
-            begin
-              debug_delay_reg <= debug_delay_new;
-            end
+            debug_delay_reg <= debug_delay_new;
         end
     end // reg_update
 
@@ -497,15 +497,15 @@ module trng(
   //----------------------------------------------------------------
   always @*
     begin : trng_api_logic
-      discard_new        = 0;
-      test_mode_new      = 0;
-      test_mode_we       = 0;
-      debug_mux_new      = 3'h0;
-      debug_mux_we       = 0;
-      debug_delay_new    = 32'h00000000;
-      debug_delay_we     = 0;
-      trng_api_read_data = 32'h00000000;
-      trng_api_error     = 0;
+      discard_new            = 0;
+      test_mode_new          = 0;
+      test_mode_we           = 0;
+      debug_mux_new          = 3'h0;
+      debug_mux_we           = 0;
+      debug_delay_new        = 32'h00000000;
+      debug_delay_we         = 0;
+      trng_api_read_data_new = 32'h00000000;
+      trng_api_error         = 0;
 
       if (trng_api_cs)
         begin
@@ -547,17 +547,17 @@ module trng(
                 // Read operations.
                 ADDR_NAME0:
                   begin
-                    trng_api_read_data = TRNG_NAME0;
+                    trng_api_read_data_new = TRNG_NAME0;
                   end
 
                 ADDR_NAME1:
                   begin
-                    trng_api_read_data = TRNG_NAME1;
+                    trng_api_read_data_new = TRNG_NAME1;
                   end
 
                 ADDR_VERSION:
                   begin
-                    trng_api_read_data = TRNG_VERSION;
+                    trng_api_read_data_new = TRNG_VERSION;
                   end
 
                 ADDR_TRNG_CTRL:
@@ -571,12 +571,12 @@ module trng(
 
                 ADDR_DEBUG_CTRL:
                   begin
-                    trng_api_read_data = debug_mux_new;
+                    trng_api_read_data_new = {29'h0000000, debug_mux_new};
                   end
 
                 ADDR_DEBUG_DELAY:
                   begin
-                    trng_api_read_data = debug_delay_reg;
+                    trng_api_read_data_new = debug_delay_reg;
                   end
 
                 default:
@@ -588,11 +588,6 @@ module trng(
         end
     end // trng_api_logic
 
-   always @(posedge clk)
-     begin
-        trng_api_read_data_reg <= trng_api_read_data;
-     end
-
 endmodule // trng
 
 //======================================================================