Fixed build and lint warnings. Cleaned up constant declarations. Changed asynch reset that collidsed with sync reset in other modules.

6 files changed, 39 insertions, 76 deletions

diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v
index c682f27..85039ad 100644
--- a/src/rtl/trng_csprng.v
+++ b/src/rtl/trng_csprng.v
@@ -277,17 +277,17 @@ module trng_csprng(
   // All registers are positive edge triggered with synchronous
   // active low reset. All registers have write enable.
   //----------------------------------------------------------------
-  always @ (posedge clk or negedge reset_n)
+  always @ (posedge clk)
     begin
       if (!reset_n)
         begin
-          cipher_key_reg      <= {8{32'h00000000}};
-          cipher_iv_reg       <= {2{32'h00000000}};
-          cipher_ctr_reg      <= {2{32'h00000000}};
-          cipher_block_reg    <= {16{32'h00000000}};
-          block_ctr_reg       <= {2{32'h00000000}};
-          block_stat_ctr_reg  <= {2{32'h00000000}};
-          reseed_stat_ctr_reg <= 32'h00000000;
+          cipher_key_reg      <= {256'h0};
+          cipher_iv_reg       <= {64'h0};
+          cipher_ctr_reg      <= {64'h0};
+          cipher_block_reg    <= {512'h0};
+          block_ctr_reg       <= {64'h00};
+          block_stat_ctr_reg  <= {64'h0};
+          reseed_stat_ctr_reg <= 32'h0;
           more_seed_reg       <= 0;
           seed_ack_reg        <= 0;
           ready_reg           <= 0;
diff --git a/src/rtl/trng_csprng_fifo.v b/src/rtl/trng_csprng_fifo.v
index db0a1be..a58af0a 100644
--- a/src/rtl/trng_csprng_fifo.v
+++ b/src/rtl/trng_csprng_fifo.v
@@ -57,7 +57,7 @@ module trng_csprng_fifo(
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
   localparam FIFO_ADDR_BITS = 2;
-  localparam FIFO_ADDR_MAX  = (2**FIFO_ADDR_BITS) - 1;
+  localparam FIFO_ADDR_MAX  = (2 ** FIFO_ADDR_BITS) - 1;
   localparam FIFO_MAX       = (2 ** FIFO_ADDR_BITS);
 
   localparam WR_IDLE    = 0;
@@ -141,19 +141,19 @@ module trng_csprng_fifo(
   //
   // Register update. All registers have asynchronous reset.
   //----------------------------------------------------------------
-  always @ (posedge clk or negedge reset_n)
+  always @ (posedge clk)
     begin
       if (!reset_n)
         begin
-          fifo_mem[00]     <= {16{32'h00000000}};
-          fifo_mem[01]     <= {16{32'h00000000}};
-          fifo_mem[02]     <= {16{32'h00000000}};
-          fifo_mem[03]     <= {16{32'h00000000}};
+          fifo_mem[00]     <= {512'h0};
+          fifo_mem[01]     <= {512'h0};
+          fifo_mem[02]     <= {512'h0};
+          fifo_mem[03]     <= {512'h0};
           mux_data_ptr_reg <= 4'h0;
           rd_ptr_reg       <= {(FIFO_ADDR_BITS){1'b0}};
           wr_ptr_reg       <= {(FIFO_ADDR_BITS){1'b0}};
           fifo_ctr_reg     <= {FIFO_ADDR_BITS{1'b0}};
-          rnd_data_reg     <= 32'h00000000;
+          rnd_data_reg     <= 32'h0;
           rnd_syn_reg      <= 0;
           more_data_reg    <= 0;
           wr_ctrl_reg      <= WR_IDLE;
diff --git a/src/tb/tb_csprng.v b/src/tb/tb_csprng.v
index 3b4d787..7c8772c 100644
--- a/src/tb/tb_csprng.v
+++ b/src/tb/tb_csprng.v
@@ -37,11 +37,6 @@
 //
 //======================================================================
 
-//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
 
 //------------------------------------------------------------------
 // Test module.
@@ -178,7 +173,7 @@ module tb_csprng();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("cycle: 0x%016x", cycle_ctr);
       $display("State of DUT");
@@ -272,7 +267,7 @@ module tb_csprng();
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -289,7 +284,7 @@ module tb_csprng();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_results();
+  task display_test_results;
     begin
       if (error_ctr == 0)
         begin
@@ -310,7 +305,7 @@ module tb_csprng();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr       = 0;
       error_ctr       = 0;
@@ -396,7 +391,7 @@ module tb_csprng();
   // enable is set. We also starts pulling random data from the
   // csprng to see that it actually emits data as expected.
   //----------------------------------------------------------------
-  task tc1_init_csprng();
+  task tc1_init_csprng;
     begin
       tc_ctr = tc_ctr + 1;
 
@@ -419,7 +414,7 @@ module tb_csprng();
   // TC2: Test that the CSPRNG is reseeded as expected.
   // We set the max block size to a small value and pull data.
   //----------------------------------------------------------------
-  task tc2_reseed_csprng();
+  task tc2_reseed_csprng;
     begin
       tc_ctr = tc_ctr + 1;
 
diff --git a/src/tb/tb_csprng_fifo.v b/src/tb/tb_csprng_fifo.v
index a2db466..db598f5 100644
--- a/src/tb/tb_csprng_fifo.v
+++ b/src/tb/tb_csprng_fifo.v
@@ -36,11 +36,6 @@
 //
 //======================================================================
 
-//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
 
 //------------------------------------------------------------------
 // Test module.
@@ -138,7 +133,7 @@ module tb_csprng_fifo();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("cycle: 0x%016x", cycle_ctr);
       $display("State of DUT");
@@ -166,7 +161,7 @@ module tb_csprng_fifo();
   //
   // Dump the state of the fifo when needed.
   //----------------------------------------------------------------
-  task dump_fifo();
+  task dump_fifo;
     begin
       $display("contents of the fifo");
       $display("--------------------");
@@ -181,28 +176,11 @@ module tb_csprng_fifo();
 
 
   //----------------------------------------------------------------
-  // gen_csprng_data
-  //
-  // Generate test data with distinct patterns as requested
-  // by the dut.
-  //----------------------------------------------------------------
-//  always @ (posedge tb_more_data)
-//    begin
-//      for (i = 0 ; i < 16 ; i = i + 1)
-//        tb_csprng_data[i * 32 +: 32] = tb_csprng_data[i * 32 +: 32] + 32'h10101010;
-//
-//      tb_csprng_data_valid = 1'b1;
-//      #(2 * CLK_PERIOD);
-//      tb_csprng_data_valid = 1'b0;
-//    end
-
-
-  //----------------------------------------------------------------
   // reset_dut()
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -219,7 +197,7 @@ module tb_csprng_fifo();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_results();
+  task display_test_results;
     begin
       if (error_ctr == 0)
         begin
@@ -240,7 +218,7 @@ module tb_csprng_fifo();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr       = 0;
       error_ctr       = 0;
@@ -269,7 +247,7 @@ module tb_csprng_fifo();
   //
   // Wait for the DUT to signal that it wants more data.
   //----------------------------------------------------------------
-  task wait_more_data();
+  task wait_more_data;
     begin
       while (!tb_more_data)
         #(CLK_PERIOD);
@@ -341,7 +319,7 @@ module tb_csprng_fifo();
   //
   // read a 32 bit data word from the fifo.
   //----------------------------------------------------------------
-  task read_w32();
+  task read_w32;
     begin
       $display("*** Reading from the fifo: 0x%08x", tb_rnd_data);
       tb_rnd_ack = 1;
@@ -359,7 +337,7 @@ module tb_csprng_fifo();
   // extracts 32-bit words and checks that we get the correct
   // words all the time.
   //----------------------------------------------------------------
-  task fifo_test();
+  task fifo_test;
     reg [7 : 0] i;
     reg [7 : 0] j;
 
diff --git a/src/tb/tb_mixer.v b/src/tb/tb_mixer.v
index 3964197..3713965 100644
--- a/src/tb/tb_mixer.v
+++ b/src/tb/tb_mixer.v
@@ -36,11 +36,6 @@
 //
 //======================================================================
 
-//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
 
 //------------------------------------------------------------------
 // Test module.
@@ -178,7 +173,7 @@ module tb_mixer();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("cycle: 0x%016x", cycle_ctr);
       $display("State of DUT");
@@ -243,7 +238,7 @@ module tb_mixer();
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -260,7 +255,7 @@ module tb_mixer();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_results();
+  task display_test_results;
     begin
       if (error_ctr == 0)
         begin
@@ -281,7 +276,7 @@ module tb_mixer();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr           = 0;
       error_ctr           = 0;
@@ -321,7 +316,7 @@ module tb_mixer();
   // A simple first testcase that tries to make the DUT generate
   // a number of seeds based on entropy from source 0 and 2.
   //----------------------------------------------------------------
-  task tc1_gen_seeds();
+  task tc1_gen_seeds;
     begin
       $display("*** Starting TC1: Setting continious seed generation.");
       tb_entropy0_enabled = 1;
diff --git a/src/tb/tb_trng.v b/src/tb/tb_trng.v
index 38d2559..27097bc 100644
--- a/src/tb/tb_trng.v
+++ b/src/tb/tb_trng.v
@@ -36,11 +36,6 @@
 //
 //======================================================================
 
-//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
 
 //------------------------------------------------------------------
 // Test module.
@@ -182,7 +177,7 @@ module tb_trng();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("cycle: 0x%016x", cycle_ctr);
       $display("State of DUT");
@@ -247,7 +242,7 @@ module tb_trng();
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -264,7 +259,7 @@ module tb_trng();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_results();
+  task display_test_results;
     begin
       if (error_ctr == 0)
         begin
@@ -285,7 +280,7 @@ module tb_trng();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr          = 0;
       error_ctr          = 0;
@@ -310,7 +305,7 @@ module tb_trng();
   // A simple first testcase that tries to make the DUT generate
   // a number of random values.
   //----------------------------------------------------------------
-  task tc1_gen_rnd();
+  task tc1_gen_rnd;
     reg [31 : 0] i;
 
     begin