Changed separate block register to reg array.new_mixer

1 files changed, 19 insertions, 282 deletions

diff --git a/src/rtl/trng_mixer.v b/src/rtl/trng_mixer.v
index 06e3323..06e014a 100644
--- a/src/rtl/trng_mixer.v
+++ b/src/rtl/trng_mixer.v
@@ -120,70 +120,7 @@ module trng_mixer(
   //----------------------------------------------------------------
   // Registers including update variables and write enable.
   //----------------------------------------------------------------
-  reg [31 : 0] block00_reg;
-  reg          block00_we;
-  reg [31 : 0] block01_reg;
-  reg          block01_we;
-  reg [31 : 0] block02_reg;
-  reg          block02_we;
-  reg [31 : 0] block03_reg;
-  reg          block03_we;
-  reg [31 : 0] block04_reg;
-  reg          block04_we;
-  reg [31 : 0] block05_reg;
-  reg          block05_we;
-  reg [31 : 0] block06_reg;
-  reg          block06_we;
-  reg [31 : 0] block07_reg;
-  reg          block07_we;
-  reg [31 : 0] block08_reg;
-  reg          block08_we;
-  reg [31 : 0] block09_reg;
-  reg          block09_we;
-  reg [31 : 0] block10_reg;
-  reg          block10_we;
-  reg [31 : 0] block11_reg;
-  reg          block11_we;
-  reg [31 : 0] block12_reg;
-  reg          block12_we;
-  reg [31 : 0] block13_reg;
-  reg          block13_we;
-  reg [31 : 0] block14_reg;
-  reg          block14_we;
-  reg [31 : 0] block15_reg;
-  reg          block15_we;
-  reg [31 : 0] block16_reg;
-  reg          block16_we;
-  reg [31 : 0] block17_reg;
-  reg          block17_we;
-  reg [31 : 0] block18_reg;
-  reg          block18_we;
-  reg [31 : 0] block19_reg;
-  reg          block19_we;
-  reg [31 : 0] block20_reg;
-  reg          block20_we;
-  reg [31 : 0] block21_reg;
-  reg          block21_we;
-  reg [31 : 0] block22_reg;
-  reg          block22_we;
-  reg [31 : 0] block23_reg;
-  reg          block23_we;
-  reg [31 : 0] block24_reg;
-  reg          block24_we;
-  reg [31 : 0] block25_reg;
-  reg          block25_we;
-  reg [31 : 0] block26_reg;
-  reg          block26_we;
-  reg [31 : 0] block27_reg;
-  reg          block27_we;
-  reg [31 : 0] block28_reg;
-  reg          block28_we;
-  reg [31 : 0] block29_reg;
-  reg          block29_we;
-  reg [31 : 0] block30_reg;
-  reg          block30_we;
-  reg [31 : 0] block31_reg;
-  reg          block31_we;
+  reg [31 : 0] block_mem [0 : 31];
 
   reg [4 : 0] word_ctr_reg;
   reg [4 : 0] word_ctr_new;
@@ -265,19 +202,17 @@ module trng_mixer(
   assign seed_syn  = seed_syn_reg;
   assign seed_data = hash_digest;
 
-  assign hash_block = {block00_reg, block01_reg, block02_reg, block03_reg,
-                       block04_reg, block05_reg, block06_reg, block07_reg,
-                       block08_reg, block09_reg,
-                       block10_reg, block11_reg, block12_reg, block13_reg,
-                       block14_reg, block15_reg, block16_reg, block17_reg,
-                       block18_reg, block19_reg,
-                       block20_reg, block21_reg, block22_reg, block23_reg,
-                       block24_reg, block25_reg, block26_reg, block27_reg,
-                       block28_reg, block29_reg,
-                       block30_reg, block31_reg};
+  assign hash_block = {block_mem[00], block_mem[01], block_mem[02], block_mem[03],
+                       block_mem[04], block_mem[05], block_mem[06], block_mem[07],
+                       block_mem[08], block_mem[09], block_mem[10], block_mem[11],
+                       block_mem[12], block_mem[13], block_mem[14], block_mem[15],
+                       block_mem[16], block_mem[17], block_mem[18], block_mem[19],
+                       block_mem[20], block_mem[21], block_mem[22], block_mem[23],
+                       block_mem[24], block_mem[25], block_mem[26], block_mem[27],
+                       block_mem[28], block_mem[29], block_mem[30], block_mem[31]};
 
   assign hash_work_factor     = 0;
-  assign hash_work_factor_num = 32'h00000000;
+  assign hash_work_factor_num = 32'h0;
 
   assign entropy0_ack = tmp_entropy0_ack;
   assign entropy1_ack = tmp_entropy1_ack;
@@ -316,41 +251,14 @@ module trng_mixer(
   // active low reset.
   //----------------------------------------------------------------
   always @ (posedge clk or negedge reset_n)
-    begin
+    begin : reg_update
+      integer i;
+
       if (!reset_n)
         begin
-          block00_reg              <= 32'h00000000;
-          block01_reg              <= 32'h00000000;
-          block02_reg              <= 32'h00000000;
-          block03_reg              <= 32'h00000000;
-          block04_reg              <= 32'h00000000;
-          block05_reg              <= 32'h00000000;
-          block06_reg              <= 32'h00000000;
-          block07_reg              <= 32'h00000000;
-          block08_reg              <= 32'h00000000;
-          block09_reg              <= 32'h00000000;
-          block10_reg              <= 32'h00000000;
-          block11_reg              <= 32'h00000000;
-          block12_reg              <= 32'h00000000;
-          block13_reg              <= 32'h00000000;
-          block14_reg              <= 32'h00000000;
-          block15_reg              <= 32'h00000000;
-          block16_reg              <= 32'h00000000;
-          block17_reg              <= 32'h00000000;
-          block18_reg              <= 32'h00000000;
-          block19_reg              <= 32'h00000000;
-          block20_reg              <= 32'h00000000;
-          block21_reg              <= 32'h00000000;
-          block22_reg              <= 32'h00000000;
-          block23_reg              <= 32'h00000000;
-          block24_reg              <= 32'h00000000;
-          block25_reg              <= 32'h00000000;
-          block26_reg              <= 32'h00000000;
-          block27_reg              <= 32'h00000000;
-          block28_reg              <= 32'h00000000;
-          block29_reg              <= 32'h00000000;
-          block30_reg              <= 32'h00000000;
-          block31_reg              <= 32'h00000000;
+          for (i = 0 ; i < 32 ; i = i + 1)
+            block_mem[i] <= 32'h0;
+
           init_done_reg            <= 0;
           word_ctr_reg             <= 5'h00;
           seed_syn_reg             <= 0;
@@ -365,101 +273,8 @@ module trng_mixer(
         begin
           restart_reg <= restart_new;
 
-          if (block00_we)
-            block00_reg <= muxed_entropy;
-
-          if (block01_we)
-            block01_reg <= muxed_entropy;
-
-          if (block02_we)
-            block02_reg <= muxed_entropy;
-
-          if (block03_we)
-            block03_reg <= muxed_entropy;
-
-          if (block04_we)
-            block04_reg <= muxed_entropy;
-
-          if (block05_we)
-            block05_reg <= muxed_entropy;
-
-          if (block06_we)
-            block06_reg <= muxed_entropy;
-
-          if (block07_we)
-            block07_reg <= muxed_entropy;
-
-          if (block08_we)
-            block08_reg <= muxed_entropy;
-
-          if (block09_we)
-            block09_reg <= muxed_entropy;
-
-          if (block10_we)
-            block10_reg <= muxed_entropy;
-
-          if (block11_we)
-            block11_reg <= muxed_entropy;
-
-          if (block12_we)
-            block12_reg <= muxed_entropy;
-
-          if (block13_we)
-            block13_reg <= muxed_entropy;
-
-          if (block14_we)
-            block14_reg <= muxed_entropy;
-
-          if (block15_we)
-            block15_reg <= muxed_entropy;
-
-          if (block16_we)
-            block16_reg <= muxed_entropy;
-
-          if (block17_we)
-            block17_reg <= muxed_entropy;
-
-          if (block18_we)
-            block18_reg <= muxed_entropy;
-
-          if (block19_we)
-            block19_reg <= muxed_entropy;
-
-          if (block20_we)
-            block20_reg <= muxed_entropy;
-
-          if (block21_we)
-            block21_reg <= muxed_entropy;
-
-          if (block22_we)
-            block22_reg <= muxed_entropy;
-
-          if (block23_we)
-            block23_reg <= muxed_entropy;
-
-          if (block24_we)
-            block24_reg <= muxed_entropy;
-
-          if (block25_we)
-            block25_reg <= muxed_entropy;
-
-          if (block26_we)
-            block26_reg <= muxed_entropy;
-
-          if (block27_we)
-            block27_reg <= muxed_entropy;
-
-          if (block28_we)
-            block28_reg <= muxed_entropy;
-
-          if (block29_we)
-            block29_reg <= muxed_entropy;
-
-          if (block30_we)
-            block30_reg <= muxed_entropy;
-
-          if (block31_we)
-            block31_reg <= muxed_entropy;
+          if (update_block)
+            block_mem[word_ctr_reg] <= muxed_entropy;
 
           if (init_done_we)
             init_done_reg <= init_done_new;
@@ -583,7 +398,7 @@ module trng_mixer(
       word_ctr_rst             = 0;
       update_block             = 0;
       block_done               = 0;
-      muxed_entropy            = 32'h00000000;
+      muxed_entropy            = 32'h0;
       entropy_timeout_ctr_inc  = 0;
       entropy_timeout_ctr_rst  = 0;
       entropy_collect_ctrl_new = ENTROPY_IDLE;
@@ -803,84 +618,6 @@ module trng_mixer(
 
 
   //----------------------------------------------------------------
-  // word_mux
-  //----------------------------------------------------------------
-  always @*
-    begin : word_mux
-      block00_we = 0;
-      block01_we = 0;
-      block02_we = 0;
-      block03_we = 0;
-      block04_we = 0;
-      block05_we = 0;
-      block06_we = 0;
-      block07_we = 0;
-      block08_we = 0;
-      block09_we = 0;
-      block10_we = 0;
-      block11_we = 0;
-      block12_we = 0;
-      block13_we = 0;
-      block14_we = 0;
-      block15_we = 0;
-      block16_we = 0;
-      block17_we = 0;
-      block18_we = 0;
-      block19_we = 0;
-      block20_we = 0;
-      block21_we = 0;
-      block22_we = 0;
-      block23_we = 0;
-      block24_we = 0;
-      block25_we = 0;
-      block26_we = 0;
-      block27_we = 0;
-      block28_we = 0;
-      block29_we = 0;
-      block30_we = 0;
-      block31_we = 0;
-
-      if (update_block)
-        begin
-          case (word_ctr_reg)
-            00 : block00_we = 1;
-            01 : block01_we = 1;
-            02 : block02_we = 1;
-            03 : block03_we = 1;
-            04 : block04_we = 1;
-            05 : block05_we = 1;
-            06 : block06_we = 1;
-            07 : block07_we = 1;
-            08 : block08_we = 1;
-            09 : block09_we = 1;
-            10 : block10_we = 1;
-            11 : block11_we = 1;
-            12 : block12_we = 1;
-            13 : block13_we = 1;
-            14 : block14_we = 1;
-            15 : block15_we = 1;
-            16 : block16_we = 1;
-            17 : block17_we = 1;
-            18 : block18_we = 1;
-            19 : block19_we = 1;
-            20 : block20_we = 1;
-            21 : block21_we = 1;
-            22 : block22_we = 1;
-            23 : block23_we = 1;
-            24 : block24_we = 1;
-            25 : block25_we = 1;
-            26 : block26_we = 1;
-            27 : block27_we = 1;
-            28 : block28_we = 1;
-            29 : block29_we = 1;
-            30 : block30_we = 1;
-            31 : block31_we = 1;
-          endcase // case (word_ctr_reg)
-        end
-    end // word_mux
-
-
-  //----------------------------------------------------------------
   // entropy_timeout_logic
   //
   // Logic that updates the entropy timeout counter and signals