Adding testbench for the complete trng.

1 files changed, 245 insertions, 0 deletions

diff --git a/src/tb/tb_trng.v b/src/tb/tb_trng.v
new file mode 100644
index 0000000..704d4ea
--- /dev/null
+++ b/src/tb/tb_trng.v
@@ -0,0 +1,245 @@
+//======================================================================
+//
+// tb_trng.v
+// -----------
+// Testbench for the trng module in the trng.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+//   this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+//------------------------------------------------------------------
+// Simulator directives.
+//------------------------------------------------------------------
+`timescale 1ns/100ps
+
+
+//------------------------------------------------------------------
+// Test module.
+//------------------------------------------------------------------
+module tb_trng();
+
+  //----------------------------------------------------------------
+  // Internal constant and parameter definitions.
+  //----------------------------------------------------------------
+  parameter DEBUG     = 1;
+
+  parameter CLK_HALF_PERIOD = 1;
+  parameter CLK_PERIOD      = 2 * CLK_HALF_PERIOD;
+
+
+  //----------------------------------------------------------------
+  // Register and Wire declarations.
+  //----------------------------------------------------------------
+  reg [31 : 0]  cycle_ctr;
+  reg [31 : 0]  error_ctr;
+  reg [31 : 0]  tc_ctr;
+
+  reg           tb_clk;
+  reg           tb_reset_n;
+  reg           tb_avalanche_noise;
+  reg           tb_cs;
+  reg           tb_we;
+  reg [7  : 0]  tb_address;
+  reg [31 : 0]  tb_write_data;
+  wire [31 : 0] tb_read_data;
+  wire          tb_error;
+  wire          tb_security_error;
+
+
+  //----------------------------------------------------------------
+  // Device Under Test.
+  //----------------------------------------------------------------
+  trng dut(
+           .clk(tb_ckl),
+           .reset_n(tb_reset_n),
+           .avalanche_noise(tb_avalanche_noise),
+           .cs(tb_cs),
+           .we(tb_we),
+           .address(tb_address),
+           .write_data(tb_write_data),
+           .read_data(tb_read_data),
+           .error(tb_error),
+           .security_error(tb_security_error)
+          );
+
+
+  //----------------------------------------------------------------
+  // clk_gen
+  //
+  // Always running clock generator process.
+  //----------------------------------------------------------------
+  always
+    begin : clk_gen
+      #CLK_HALF_PERIOD;
+      tb_clk = !tb_clk;
+    end // clk_gen
+
+
+  //----------------------------------------------------------------
+  // sys_monitor()
+  //
+  // An always running process that creates a cycle counter and
+  // conditionally displays information about the DUT.
+  //----------------------------------------------------------------
+  always
+    begin : sys_monitor
+      cycle_ctr = cycle_ctr + 1;
+
+      #(CLK_PERIOD);
+
+      if (DEBUG)
+        begin
+          dump_dut_state();
+        end
+    end
+
+
+  //----------------------------------------------------------------
+  // dump_dut_state()
+  //
+  // Dump the state of the dump when needed.
+  //----------------------------------------------------------------
+  task dump_dut_state();
+    begin
+      $display("cycle: 0x%016x", cycle_ctr);
+      $display("State of DUT");
+      $display("------------");
+      $display("");
+    end
+  endtask // dump_dut_state
+
+
+  //----------------------------------------------------------------
+  // reset_dut()
+  //
+  // Toggle reset to put the DUT into a well known state.
+  //----------------------------------------------------------------
+  task reset_dut();
+    begin
+      $display("*** Toggle reset.");
+      tb_reset_n = 0;
+
+      #(2 * CLK_PERIOD);
+      tb_reset_n = 1;
+      $display("");
+    end
+  endtask // reset_dut
+
+
+  //----------------------------------------------------------------
+  // display_test_results()
+  //
+  // Display the accumulated test results.
+  //----------------------------------------------------------------
+  task display_test_results();
+    begin
+      if (error_ctr == 0)
+        begin
+          $display("*** All %02d test cases completed successfully", tc_ctr);
+        end
+      else
+        begin
+          $display("*** %02d tests completed - %02d test cases did not complete successfully.",
+                   tc_ctr, error_ctr);
+        end
+    end
+  endtask // display_test_results
+
+
+  //----------------------------------------------------------------
+  // init_sim()
+  //
+  // Initialize all counters and testbed functionality as well
+  // as setting the DUT inputs to defined values.
+  //----------------------------------------------------------------
+  task init_sim();
+    begin
+      cycle_ctr           = 0;
+      error_ctr           = 0;
+      tc_ctr              = 0;
+
+      tb_clk              = 0;
+      tb_reset_n          = 1;
+
+    end
+  endtask // init_sim
+
+
+  //----------------------------------------------------------------
+  // tc1_gen_rnd()
+  //
+  // A simple first testcase that tries to make the DUT generate
+  // a number of seeds based on entropy from source 0 and 2.
+  //----------------------------------------------------------------
+  task tc1_gen_rnd();
+    begin
+      $display("*** Starting TC1: Generating random values from entropy.");
+
+
+      #(50000 * CLK_PERIOD);
+
+
+      $display("*** TC1 done.");
+    end
+  endtask // tc1_gen_seeds
+
+
+  //----------------------------------------------------------------
+  // trng_test
+  //
+  // The main test functionality.
+  //----------------------------------------------------------------
+  initial
+    begin : trng_test
+
+      $display("   -= Testbench for TRNG started =-");
+      $display("    ===============================");
+      $display("");
+
+      init_sim();
+      dump_dut_state();
+      reset_dut();
+      dump_dut_state();
+
+      tc1_gen_rnd();
+
+      display_test_results();
+
+      $display("");
+      $display("*** TRNG simulation done. ***");
+      $finish;
+    end // trng_test
+endmodule // tb_trng
+
+//======================================================================
+// EOF tb_trng.v
+//======================================================================