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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-05-22 10:34:50 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-05-22 10:34:50 +0200
commitd5974ed0d389f8953b23d98bb69b1576adad27b8 (patch)
treee604e1ade476afbb3e312d3d923d1ec62fcf2913 /src/tb
parent92790f3b539f275a060ca6bd4e2d91a9e5b13718 (diff)
(1) Added a cipher block statistics counter. (2) Cleaned up the csprng code and connected discard for fast restart of trng. (3) Added addresses for allowing API to write a known seed to allow test mode. (3) Fixed a number of minor issues during linting. (4) Fixed the csprng testbench to actually generate data as well as displaying the block stat counter.
Diffstat (limited to 'src/tb')
-rw-r--r--src/tb/fake_modules/avalanche_entropy.v4
-rw-r--r--src/tb/fake_modules/rosc_entropy.v6
-rw-r--r--src/tb/tb_csprng.v67
3 files changed, 50 insertions, 27 deletions
diff --git a/src/tb/fake_modules/avalanche_entropy.v b/src/tb/fake_modules/avalanche_entropy.v
index 857926c..2caf743 100644
--- a/src/tb/fake_modules/avalanche_entropy.v
+++ b/src/tb/fake_modules/avalanche_entropy.v
@@ -80,9 +80,9 @@ module avalanche_entropy(
.clk(clk),
.reset_n(reset_n),
- .enable(1),
+ .enable(1'b1),
- .raw_entropy(noise),
+ .raw_entropy(),
.stats(),
.enabled(entropy_enabled),
diff --git a/src/tb/fake_modules/rosc_entropy.v b/src/tb/fake_modules/rosc_entropy.v
index b66bd90..add8b7a 100644
--- a/src/tb/fake_modules/rosc_entropy.v
+++ b/src/tb/fake_modules/rosc_entropy.v
@@ -41,8 +41,6 @@ module rosc_entropy(
input wire clk,
input wire reset_n,
- input wire noise,
-
input wire cs,
input wire we,
input wire [7 : 0] address,
@@ -80,9 +78,9 @@ module rosc_entropy(
.clk(clk),
.reset_n(reset_n),
- .enable(1),
+ .enable(1'b1),
- .raw_entropy(noise),
+ .raw_entropy(),
.stats(),
.enabled(entropy_enabled),
diff --git a/src/tb/tb_csprng.v b/src/tb/tb_csprng.v
index f860258..0404b56 100644
--- a/src/tb/tb_csprng.v
+++ b/src/tb/tb_csprng.v
@@ -55,6 +55,25 @@ module tb_csprng();
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
+ localparam ADDR_NAME0 = 8'h00;
+ localparam ADDR_NAME1 = 8'h01;
+ localparam ADDR_VERSION = 8'h02;
+
+ localparam ADDR_CTRL = 8'h10;
+ localparam CTRL_ENABLE_BIT = 0;
+ localparam CTRL_SEED_BIT = 1;
+
+ localparam ADDR_STATUS = 8'h11;
+ localparam STATUS_RND_VALID_BIT = 0;
+
+ localparam ADDR_STAT_BLOCKS_LOW = 8'h14;
+ localparam ADDR_STAT_BLOCKS_HIGH = 8'h15;
+
+ localparam ADDR_RND_DATA = 8'h20;
+
+ localparam ADDR_NUM_ROUNDS = 8'h40;
+ localparam ADDR_NUM_BLOCKS_LOW = 8'h41;
+ localparam ADDR_NUM_BLOCKS_HIGH = 8'h42;
//----------------------------------------------------------------
// Register and Wire declarations.
@@ -166,17 +185,19 @@ module tb_csprng();
$display("test_mode = 0x%01x, seed = 0x%01x, enable = 0x%01x",
dut.test_mode, dut.seed_reg, dut.enable_reg);
$display("num_rounds = 0x%02x, num_blocks = 0x%016x",
- dut.num_rounds_reg, dut.num_blocks);
+ dut.num_rounds_reg, {dut.num_blocks_high_reg,
+ dut.num_blocks_low_reg});
$display("seed_syn = 0x%01x, seed_ack = 0x%01x, seed_data = 0x%064x",
dut.seed_syn, dut.seed_ack, dut.seed_data);
$display("");
$display("Internal states:");
- $display("cipher_key = 0x%032x", dut.cipher_key_reg);
- $display("cipher_iv = 0x%08x, cipher_ctr = 0x%08x",
+ $display("cipher_key = 0x%032x", dut.cipher_key_reg);
+ $display("cipher_iv = 0x%08x, cipher_ctr = 0x%08x",
dut.cipher_iv_reg, dut.cipher_ctr_reg);
- $display("cipher_block = 0x%064x", dut.cipher_block_reg);
- $display("csprng_ctrl = 0x%02x", dut.csprng_ctrl_reg);
+ $display("cipher_block = 0x%064x", dut.cipher_block_reg);
+ $display("csprng_blocks = 0x%016x", dut.block_stat_ctr_reg);
+ $display("csprng_ctrl = 0x%02x", dut.csprng_ctrl_reg);
$display("");
$display("Cipher states:");
@@ -192,7 +213,7 @@ module tb_csprng();
$display("Outputs:");
$display("rnd_syn = 0x%01x, rnd_ack = 0x%01x, rnd_data = 0x%08x",
- dut.rnd_syn, dut.rnd_ack, dut.rnd_data);
+ dut.rnd_syn, dut.rnd_ack, tb_read_data);
$display("");
end
endtask // dump_dut_state
@@ -203,7 +224,7 @@ module tb_csprng();
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
- task write_word(input [11 : 0] address,
+ task write_word(input [11 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
@@ -317,25 +338,30 @@ module tb_csprng();
//----------------------------------------------------------------
- // tc1_test_init_cipher()
+ // tc1_init_csprng()
//
// TC1: Test that the DUT automatically starts initialize when
- // enable is set.
+ // enable is set. We also starts pulling random data from the
+ // csprng to see that it actually emits data as expected.
//----------------------------------------------------------------
- task tc1_test_init_cipher();
+ task tc1_init_csprng();
begin
- $display("*** TC1: Test automatic init of cipher started.");
- // tb_num_blocks = 64'h0000000000000004;
- tb_seed_data = {8{64'haaaaaaaa55555555}};
- // tb_num_rounds = 5'h08;
- tb_rnd_ack = 1;
+ tc_ctr = tc_ctr + 1;
+
+ $display("*** TC1: Test automatic init of csprng started.");
+
+ tb_seed_data = {8{64'haaaaaaaa55555555}};
+ tb_seed_syn = 1'b1;
- #(2000 * CLK_PERIOD);
+ tb_cs = 1'b1;
+ tb_we = 1'b0;
+ tb_address = ADDR_RND_DATA;
- $display("*** TC1: Test automatic init of cipher done.");
+ #(200 * CLK_PERIOD);
+ $display("*** TC1: Test automatic init of csprng done.");
end
- endtask // tc1_test_init_cipher
+ endtask // tc1_init_csprng
//----------------------------------------------------------------
@@ -355,13 +381,12 @@ module tb_csprng();
reset_dut();
dump_dut_state();
- // Test code goes here.
- tc1_test_init_cipher();
+ tc1_init_csprng();
display_test_results();
$display("");
- $display("*** CSPRNG simulation done. ***");
+ $display("*** csprng simulation done. ***");
$finish;
end // csprng_test
endmodule // tb_csprng