(1) Added a state in the write fifo machine to actually drop request between csprng data words. (2) Updated the testbench with better test vector generation.

1 files changed, 5 insertions, 7 deletions

diff --git a/src/tb/tb_csprng_fifo.v b/src/tb/tb_csprng_fifo.v
index c5e283e..91044a5 100644
--- a/src/tb/tb_csprng_fifo.v
+++ b/src/tb/tb_csprng_fifo.v
@@ -81,7 +81,8 @@ module tb_csprng_fifo();
   wire [31 : 0] tb_rnd_data;
   reg           tb_rnd_ack;
 
-  integer i;
+  reg [7 : 0]   i;
+
 
   //----------------------------------------------------------------
   // Device Under Test.
@@ -158,7 +159,7 @@ module tb_csprng_fifo();
   always @ (posedge tb_more_data)
     begin
       for (i = 0 ; i < 16 ; i = i + 1)
-        tb_csprng_data[i * 32 +: 32] = ~tb_csprng_data[i * 32 +: 32] + 32'h01010101;
+        tb_csprng_data[i * 32 +: 32] = tb_csprng_data[i * 32 +: 32] + 32'h10101010;
 
       tb_csprng_data_valid = 1'b1;
       #(2 * CLK_PERIOD);
@@ -210,8 +211,6 @@ module tb_csprng_fifo();
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
   task init_sim();
-    integer i;
-
     begin
       cycle_ctr       = 0;
       error_ctr       = 0;
@@ -229,8 +228,7 @@ module tb_csprng_fifo();
       tb_rnd_ack      = 1;
 
       for (i = 0 ; i < 16 ; i = i + 1)
-        tb_csprng_data[i * 32 +: 32] = 32'h01010101 << (i + 1);
-
+        tb_csprng_data[i * 32 +: 32] = {i, i, i, i};
     end
   endtask // init_sim
 
@@ -252,7 +250,7 @@ module tb_csprng_fifo();
       reset_dut();
       dump_dut_state();
 
-      #(100000 * CLK_PERIOD)
+      #(100 * CLK_PERIOD)
 
       display_test_results();