diff options
| author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-03-27 13:26:44 +0200 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-03-27 13:26:44 +0200 |
| commit | 56e604d14a4c4121a0f188534b1811422c165eb8 (patch) | |
| tree | 0882abf5a59936f714823940925c1a8771248711 /src/tb/tb_trng.v | |
| parent | 953909d18796c1caea35263eb902b1dd7021d92d (diff) | |
Fixed build and lint warnings. Cleaned up constant declarations. Changed asynch reset that collidsed with sync reset in other modules.
Diffstat (limited to 'src/tb/tb_trng.v')
| -rw-r--r-- | src/tb/tb_trng.v | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/src/tb/tb_trng.v b/src/tb/tb_trng.v index 38d2559..27097bc 100644 --- a/src/tb/tb_trng.v +++ b/src/tb/tb_trng.v @@ -36,11 +36,6 @@ // //====================================================================== -//------------------------------------------------------------------ -// Simulator directives. -//------------------------------------------------------------------ -`timescale 1ns/100ps - //------------------------------------------------------------------ // Test module. @@ -182,7 +177,7 @@ module tb_trng(); // // Dump the state of the dump when needed. //---------------------------------------------------------------- - task dump_dut_state(); + task dump_dut_state; begin $display("cycle: 0x%016x", cycle_ctr); $display("State of DUT"); @@ -247,7 +242,7 @@ module tb_trng(); // // Toggle reset to put the DUT into a well known state. //---------------------------------------------------------------- - task reset_dut(); + task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; @@ -264,7 +259,7 @@ module tb_trng(); // // Display the accumulated test results. //---------------------------------------------------------------- - task display_test_results(); + task display_test_results; begin if (error_ctr == 0) begin @@ -285,7 +280,7 @@ module tb_trng(); // Initialize all counters and testbed functionality as well // as setting the DUT inputs to defined values. //---------------------------------------------------------------- - task init_sim(); + task init_sim; begin cycle_ctr = 0; error_ctr = 0; @@ -310,7 +305,7 @@ module tb_trng(); // A simple first testcase that tries to make the DUT generate // a number of random values. //---------------------------------------------------------------- - task tc1_gen_rnd(); + task tc1_gen_rnd; reg [31 : 0] i; begin |