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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-10-16 11:13:50 +0200 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-10-16 11:13:50 +0200 |
| commit | e786303f0d2778f7c26cbb443831823c82429205 (patch) | |
| tree | f8e9ff5c14890ed309a643b3e857c0d52a33c53c /src/tb/tb_trng.v | |
| parent | 6397d9766e802b2fba115a47e0f0561fcc7e828f (diff) | |
(1) Fixed width definitions and cleaned up constants as part of checking that all registers are being reset. (2) Cleaned up tasks and removed timescale directives to silence lint.HEADmaster
Diffstat (limited to 'src/tb/tb_trng.v')
| -rw-r--r-- | src/tb/tb_trng.v | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/src/tb/tb_trng.v b/src/tb/tb_trng.v index 38d2559..16d88de 100644 --- a/src/tb/tb_trng.v +++ b/src/tb/tb_trng.v @@ -37,12 +37,6 @@ //====================================================================== //------------------------------------------------------------------ -// Simulator directives. -//------------------------------------------------------------------ -`timescale 1ns/100ps - - -//------------------------------------------------------------------ // Test module. //------------------------------------------------------------------ module tb_trng(); @@ -182,7 +176,7 @@ module tb_trng(); // // Dump the state of the dump when needed. //---------------------------------------------------------------- - task dump_dut_state(); + task dump_dut_state; begin $display("cycle: 0x%016x", cycle_ctr); $display("State of DUT"); @@ -247,7 +241,7 @@ module tb_trng(); // // Toggle reset to put the DUT into a well known state. //---------------------------------------------------------------- - task reset_dut(); + task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; @@ -264,7 +258,7 @@ module tb_trng(); // // Display the accumulated test results. //---------------------------------------------------------------- - task display_test_results(); + task display_test_results; begin if (error_ctr == 0) begin @@ -285,7 +279,7 @@ module tb_trng(); // Initialize all counters and testbed functionality as well // as setting the DUT inputs to defined values. //---------------------------------------------------------------- - task init_sim(); + task init_sim; begin cycle_ctr = 0; error_ctr = 0; @@ -310,7 +304,7 @@ module tb_trng(); // A simple first testcase that tries to make the DUT generate // a number of random values. //---------------------------------------------------------------- - task tc1_gen_rnd(); + task tc1_gen_rnd; reg [31 : 0] i; begin |