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authorJoachim StroĢˆmbergson <joachim@secworks.se>2018-03-27 13:26:44 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2018-03-27 13:26:44 +0200
commit56e604d14a4c4121a0f188534b1811422c165eb8 (patch)
tree0882abf5a59936f714823940925c1a8771248711 /src/tb/tb_csprng.v
parent953909d18796c1caea35263eb902b1dd7021d92d (diff)
Fixed build and lint warnings. Cleaned up constant declarations. Changed asynch reset that collidsed with sync reset in other modules.
Diffstat (limited to 'src/tb/tb_csprng.v')
-rw-r--r--src/tb/tb_csprng.v17
1 files changed, 6 insertions, 11 deletions
diff --git a/src/tb/tb_csprng.v b/src/tb/tb_csprng.v
index 3b4d787..7c8772c 100644
--- a/src/tb/tb_csprng.v
+++ b/src/tb/tb_csprng.v
@@ -37,11 +37,6 @@
//
//======================================================================
-//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
//------------------------------------------------------------------
// Test module.
@@ -178,7 +173,7 @@ module tb_csprng();
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
- task dump_dut_state();
+ task dump_dut_state;
begin
$display("cycle: 0x%016x", cycle_ctr);
$display("State of DUT");
@@ -272,7 +267,7 @@ module tb_csprng();
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
- task reset_dut();
+ task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
@@ -289,7 +284,7 @@ module tb_csprng();
//
// Display the accumulated test results.
//----------------------------------------------------------------
- task display_test_results();
+ task display_test_results;
begin
if (error_ctr == 0)
begin
@@ -310,7 +305,7 @@ module tb_csprng();
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
- task init_sim();
+ task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
@@ -396,7 +391,7 @@ module tb_csprng();
// enable is set. We also starts pulling random data from the
// csprng to see that it actually emits data as expected.
//----------------------------------------------------------------
- task tc1_init_csprng();
+ task tc1_init_csprng;
begin
tc_ctr = tc_ctr + 1;
@@ -419,7 +414,7 @@ module tb_csprng();
// TC2: Test that the CSPRNG is reseeded as expected.
// We set the max block size to a small value and pull data.
//----------------------------------------------------------------
- task tc2_reseed_csprng();
+ task tc2_reseed_csprng;
begin
tc_ctr = tc_ctr + 1;