Fixed build and lint warnings. Cleaned up constant declarations. Changed asynch reset that collidsed with sync reset in other modules.

1 files changed, 8 insertions, 8 deletions

diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v
index c682f27..85039ad 100644
--- a/src/rtl/trng_csprng.v
+++ b/src/rtl/trng_csprng.v
@@ -277,17 +277,17 @@ module trng_csprng(
   // All registers are positive edge triggered with synchronous
   // active low reset. All registers have write enable.
   //----------------------------------------------------------------
-  always @ (posedge clk or negedge reset_n)
+  always @ (posedge clk)
     begin
       if (!reset_n)
         begin
-          cipher_key_reg      <= {8{32'h00000000}};
-          cipher_iv_reg       <= {2{32'h00000000}};
-          cipher_ctr_reg      <= {2{32'h00000000}};
-          cipher_block_reg    <= {16{32'h00000000}};
-          block_ctr_reg       <= {2{32'h00000000}};
-          block_stat_ctr_reg  <= {2{32'h00000000}};
-          reseed_stat_ctr_reg <= 32'h00000000;
+          cipher_key_reg      <= {256'h0};
+          cipher_iv_reg       <= {64'h0};
+          cipher_ctr_reg      <= {64'h0};
+          cipher_block_reg    <= {512'h0};
+          block_ctr_reg       <= {64'h00};
+          block_stat_ctr_reg  <= {64'h0};
+          reseed_stat_ctr_reg <= 32'h0;
           more_seed_reg       <= 0;
           seed_ack_reg        <= 0;
           ready_reg           <= 0;