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author | Joachim StroĢmbergson <joachim@secworks.se> | 2014-09-26 14:55:18 +0200 |
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committer | Joachim StroĢmbergson <joachim@secworks.se> | 2014-09-26 14:55:18 +0200 |
commit | f2d1d8430c9ed9923e9cd701744e705f2c91751b (patch) | |
tree | 92e2a322c319a46d903776b3d1cc515054ccbacc /src/rtl/trng_csprng.v | |
parent | 70d6aac81ec88f8140d5c644d89d3f580c1b3335 (diff) |
Updating source to the latest and greatest. In this version the entropy sources works and all modules have correct intterface.
Diffstat (limited to 'src/rtl/trng_csprng.v')
-rw-r--r-- | src/rtl/trng_csprng.v | 277 |
1 files changed, 219 insertions, 58 deletions
diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v index f9869db..a6dd247 100644 --- a/src/rtl/trng_csprng.v +++ b/src/rtl/trng_csprng.v @@ -41,25 +41,24 @@ module trng_csprng( input wire clk, input wire reset_n, - // Control, config and status. - input wire enable, - input debug_mode, - input wire [4 : 0] num_rounds, - input wire [63 : 0] num_blocks, - input wire seed, - output wire more_seed, - output wire ready, + input wire cs, + input wire we, + input wire [7 : 0] address, + input wire [31 : 0] write_data, + output wire [31 : 0] read_data, output wire error, - // Seed input + input wire discard, + input test_mode, + output wire more_seed, + output wire security_error, + input [511 : 0] seed_data, input wire seed_syn, output wire seed_ack, - // Random data output - output wire rnd_syn, - output wire [31 : 0] rnd_data, - input wire rnd_ack + output wire [7 : 0] debug, + input wire debug_update ); @@ -80,6 +79,22 @@ module trng_csprng( parameter CTRL_MORE = 4'h8; parameter CTRL_CANCEL = 4'hf; + parameter DEFAULT_NUM_ROUNDS = 5'h18; + parameter DEFAULT_NUM_BLOCKS = 64'h1000000000000000; + + parameter ADDR_CTRL = 8'h10; + parameter CTRL_ENABLE_BIT = 0; + parameter CTRL_SEED_BIT = 1; + + parameter ADDR_STATUS = 8'h11; + parameter STATUS_RND_VALID_BIT = 0; + + parameter ADDR_RND_DATA = 8'h20; + + parameter ADDR_NUM_ROUNDS = 8'h40; + parameter ADDR_NUM_BLOCK_LOW = 8'h41; + parameter ADDR_NUM_BLOCK_HIGH = 8'h42; + //---------------------------------------------------------------- // Registers including update variables and write enable. @@ -107,14 +122,6 @@ module trng_csprng( reg block_ctr_we; reg block_ctr_max; - reg error_reg; - reg error_new; - reg error_we; - - reg [3 : 0] csprng_ctrl_reg; - reg [3 : 0] csprng_ctrl_new; - reg csprng_ctrl_we; - reg ready_reg; reg ready_new; reg ready_we; @@ -125,10 +132,36 @@ module trng_csprng( reg seed_ack_reg; reg seed_ack_new; + reg enable_reg; + reg enable_new; + reg enable_we; + + reg seed_reg; + reg seed_new; + + reg [4 : 0] num_rounds_reg; + reg [4 : 0] num_rounds_new; + reg num_rounds_we; + + reg [31 : 0] num_blocks_low_reg; + reg [31 : 0] num_blocks_low_new; + reg num_blocks_low_we; + + reg [31 : 0] num_blocks_high_reg; + reg [31 : 0] num_blocks_high_new; + reg num_blocks_high_we; + + reg [3 : 0] csprng_ctrl_reg; + reg [3 : 0] csprng_ctrl_new; + reg csprng_ctrl_we; + //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- + reg [31 : 0] tmp_read_data; + reg tmp_error; + reg cipher_init; reg cipher_next; @@ -138,22 +171,25 @@ module trng_csprng( wire fifo_more_data; reg fifo_discard; - wire fifo_rnd_syn; - wire [31 : 0] fifo_rnd_data; + wire rnd_syn; + wire [31 : 0] rnd_data; + reg rnd_ack; reg fifo_cipher_data_valid; + wire [63 : 0] num_blocks; + //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- - assign seed_ack = seed_ack_reg; - assign more_seed = more_seed_reg; - - assign ready = ready_reg; - assign error = error_reg; + assign read_data = tmp_read_data; + assign error = tmp_error; + assign seed_ack = seed_ack_reg; + assign more_seed = more_seed_reg; + assign debug = 8'haa; + assign security_error = 0; - assign rnd_syn = fifo_rnd_syn; - assign rnd_data = fifo_rnd_data; + assign num_blocks = {num_blocks_high_reg, num_blocks_low_reg}; //---------------------------------------------------------------- @@ -170,7 +206,7 @@ module trng_csprng( .keylen(CIPHER_KEYLEN256), .iv(cipher_iv_reg), .ctr(cipher_ctr_reg), - .rounds(num_rounds), + .rounds(num_rounds_reg), .data_in(cipher_block_reg), .ready(cipher_ready), @@ -189,8 +225,8 @@ module trng_csprng( .discard(fifo_discard), .more_data(fifo_more_data), - .rnd_syn(fifo_rnd_syn), - .rnd_data(fifo_rnd_data), + .rnd_syn(rnd_syn), + .rnd_data(rnd_data), .rnd_ack(rnd_ack) ); @@ -206,21 +242,31 @@ module trng_csprng( begin if (!reset_n) begin - cipher_key_reg <= {8{32'h00000000}}; - cipher_iv_reg <= {2{32'h00000000}}; - cipher_ctr_reg <= {2{32'h00000000}}; - cipher_block_reg <= {16{32'h00000000}}; - block_ctr_reg <= {2{32'h00000000}}; - more_seed_reg <= 0; - seed_ack_reg <= 0; - ready_reg <= 0; - error_reg <= 0; - csprng_ctrl_reg <= CTRL_IDLE; + cipher_key_reg <= {8{32'h00000000}}; + cipher_iv_reg <= {2{32'h00000000}}; + cipher_ctr_reg <= {2{32'h00000000}}; + cipher_block_reg <= {16{32'h00000000}}; + block_ctr_reg <= {2{32'h00000000}}; + more_seed_reg <= 0; + seed_ack_reg <= 0; + ready_reg <= 0; + enable_reg <= 0; + seed_reg <= 0; + num_rounds_reg <= DEFAULT_NUM_ROUNDS; + num_blocks_low_reg <= DEFAULT_NUM_BLOCKS[31 : 0]; + num_blocks_high_reg <= DEFAULT_NUM_BLOCKS[63 : 32]; + csprng_ctrl_reg <= CTRL_IDLE; end else begin more_seed_reg <= more_seed_new; seed_ack_reg <= seed_ack_new; + seed_reg <= seed_new; + + if (enable_we) + begin + enable_reg <= enable_new; + end if (cipher_key_we) begin @@ -252,20 +298,137 @@ module trng_csprng( ready_reg <= ready_new; end - if (error_we) + if (csprng_ctrl_we) begin - error_reg <= error_new; + csprng_ctrl_reg <= csprng_ctrl_new; end - if (csprng_ctrl_we) + if (num_rounds_we) begin - csprng_ctrl_reg <= csprng_ctrl_new; + num_rounds_reg <= num_rounds_new; + end + + if (num_blocks_low_we) + begin + num_blocks_low_reg <= num_blocks_low_new; + end + + if (num_blocks_high_we) + begin + num_blocks_high_reg <= num_blocks_high_new; end end end // reg_update //---------------------------------------------------------------- + // csprng_api_logic + //---------------------------------------------------------------- + always @* + begin : csprng_api_logic + enable_new = 0; + enable_we = 0; + seed_new = 0; + + num_rounds_new = 5'h00; + num_rounds_we = 0; + + num_blocks_low_new = 32'h00000000; + num_blocks_low_we = 0; + num_blocks_high_new = 32'h00000000; + num_blocks_high_we = 0; + + rnd_ack = 0; + + tmp_read_data = 32'h00000000; + tmp_error = 0; + + if (cs) + begin + if (we) + begin + // Write operations. + case (address) + // Write operations. + ADDR_CTRL: + begin + enable_new = write_data[CTRL_ENABLE_BIT]; + enable_we = 1; + seed_new = write_data[CTRL_SEED_BIT]; + end + + ADDR_NUM_ROUNDS: + begin + num_rounds_new = write_data[4 : 0]; + num_rounds_we = 1; + end + + ADDR_NUM_BLOCK_LOW: + begin + num_blocks_low_new = write_data; + num_blocks_low_we = 1; + end + + ADDR_NUM_BLOCK_HIGH: + begin + num_blocks_high_new = write_data; + num_blocks_high_we = 1; + end + + default: + begin + tmp_error = 1; + end + endcase // case (address) + end // if (we) + + else + begin + // Read operations. + case (address) + // Read operations. + ADDR_CTRL: + begin + tmp_read_data = {30'h00000000, seed_reg, enable_reg}; + end + + ADDR_STATUS: + begin + tmp_read_data = {ready_reg, rnd_syn}; + end + + ADDR_RND_DATA: + begin + tmp_read_data = rnd_data; + rnd_ack = 1; + end + + ADDR_NUM_ROUNDS: + begin + tmp_read_data = {27'h0000000, num_rounds_reg}; + end + + ADDR_NUM_BLOCK_LOW: + begin + tmp_read_data = num_blocks_low_reg; + end + + ADDR_NUM_BLOCK_HIGH: + begin + tmp_read_data = num_blocks_high_reg; + end + + default: + begin + tmp_error = 1; + end + endcase // case (address) + end + end + end // cspng_api_logic + + + //---------------------------------------------------------------- // block_ctr // // Logic to implement the block counter. This includes the @@ -319,8 +482,6 @@ module trng_csprng( block_ctr_inc = 0; ready_new = 0; ready_we = 0; - error_new = 0; - error_we = 0; seed_ack_new = 0; more_seed_new = 0; fifo_discard = 0; @@ -331,7 +492,7 @@ module trng_csprng( case (csprng_ctrl_reg) CTRL_IDLE: begin - if (!enable) + if (!enable_reg) begin csprng_ctrl_new = CTRL_CANCEL; csprng_ctrl_we = 1; @@ -346,7 +507,7 @@ module trng_csprng( CTRL_SEED0: begin - if ((!enable) || (seed)) + if ((!enable_reg) || (seed_reg)) begin csprng_ctrl_new = CTRL_CANCEL; csprng_ctrl_we = 1; @@ -363,7 +524,7 @@ module trng_csprng( CTRL_NSYN: begin - if ((!enable) || (seed)) + if ((!enable_reg) || (seed_reg)) begin csprng_ctrl_new = CTRL_CANCEL; csprng_ctrl_we = 1; @@ -378,7 +539,7 @@ module trng_csprng( CTRL_SEED1: begin - if ((!enable) || (seed)) + if ((!enable_reg) || (seed_reg)) begin csprng_ctrl_new = CTRL_CANCEL; csprng_ctrl_we = 1; @@ -403,7 +564,7 @@ module trng_csprng( CTRL_INIT0: begin - if ((!enable) || (seed)) + if ((!enable_reg) || (seed_reg)) begin csprng_ctrl_new = CTRL_CANCEL; csprng_ctrl_we = 1; @@ -419,7 +580,7 @@ module trng_csprng( CTRL_INIT1: begin - if ((!enable) || (seed)) + if ((!enable_reg) || (seed_reg)) begin csprng_ctrl_new = CTRL_CANCEL; csprng_ctrl_we = 1; @@ -433,7 +594,7 @@ module trng_csprng( CTRL_NEXT0: begin - if ((!enable) || (seed)) + if ((!enable_reg) || (seed_reg)) begin csprng_ctrl_new = CTRL_CANCEL; csprng_ctrl_we = 1; @@ -447,7 +608,7 @@ module trng_csprng( end CTRL_NEXT1: - if ((!enable) || (seed)) + if ((!enable_reg) || (seed_reg)) begin csprng_ctrl_new = CTRL_CANCEL; csprng_ctrl_we = 1; @@ -462,7 +623,7 @@ module trng_csprng( CTRL_MORE: begin - if ((!enable) || (seed)) + if ((!enable_reg) || (seed_reg)) begin csprng_ctrl_new = CTRL_CANCEL; csprng_ctrl_we = 1; |