(1) Remove the delayed read for EIM (see core/platform/novena commit 2f58e8f). (2) Add the code to read the csprng name and version registers.

3 files changed, 37 insertions, 38 deletions

diff --git a/src/rtl/trng.v b/src/rtl/trng.v
index 15714c5..728fa39 100644
--- a/src/rtl/trng.v
+++ b/src/rtl/trng.v
@@ -123,8 +123,6 @@ module trng(
   //----------------------------------------------------------------
   wire           trng_api_cs = cs && (addr_core_num == TRNG_PREFIX);
   wire           trng_api_we = we;
-  reg [31 : 0]   trng_api_read_data_reg;
-  reg [31 : 0]   trng_api_read_data_new;
   reg [31 : 0]   trng_api_read_data;
   reg            trng_api_error;
 
@@ -343,7 +341,7 @@ module trng(
       case (address[11 : 8])
         TRNG_PREFIX:
           begin
-            tmp_read_data = trng_api_read_data_reg;
+            tmp_read_data = trng_api_read_data;
             tmp_error     = trng_api_error;
           end
 
@@ -397,16 +395,12 @@ module trng(
           debug_delay_reg        <= DEFAULT_DEBUG_DELAY;
           debug_delay_ctr_reg    <= 32'h00000000;
           debug_out_reg          <= 8'h00;
-          trng_api_read_data_reg <= 32'h00000000;
         end
       else
         begin
           discard_reg            <= discard_new;
           debug_delay_ctr_reg    <= debug_delay_ctr_new;
 
-          if (trng_api_cs)
-            trng_api_read_data_reg <= trng_api_read_data_new;
-
           if (debug_out_we)
             debug_out_reg <= tmp_debug;
 
@@ -504,7 +498,7 @@ module trng(
       debug_mux_we           = 0;
       debug_delay_new        = 32'h00000000;
       debug_delay_we         = 0;
-      trng_api_read_data_new = 32'h00000000;
+      trng_api_read_data     = 32'h00000000;
       trng_api_error         = 0;
 
       if (trng_api_cs)
@@ -547,17 +541,17 @@ module trng(
                 // Read operations.
                 ADDR_NAME0:
                   begin
-                    trng_api_read_data_new = TRNG_NAME0;
+                    trng_api_read_data = TRNG_NAME0;
                   end
 
                 ADDR_NAME1:
                   begin
-                    trng_api_read_data_new = TRNG_NAME1;
+                    trng_api_read_data = TRNG_NAME1;
                   end
 
                 ADDR_VERSION:
                   begin
-                    trng_api_read_data_new = TRNG_VERSION;
+                    trng_api_read_data = TRNG_VERSION;
                   end
 
                 ADDR_TRNG_CTRL:
@@ -571,12 +565,12 @@ module trng(
 
                 ADDR_DEBUG_CTRL:
                   begin
-                    trng_api_read_data_new = {29'h0000000, debug_mux_new};
+                    trng_api_read_data = {29'h0000000, debug_mux_new};
                   end
 
                 ADDR_DEBUG_DELAY:
                   begin
-                    trng_api_read_data_new = debug_delay_reg;
+                    trng_api_read_data = debug_delay_reg;
                   end
 
                 default:
diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v
index 1fa6135..eda9eea 100644
--- a/src/rtl/trng_csprng.v
+++ b/src/rtl/trng_csprng.v
@@ -163,8 +163,7 @@ module trng_csprng(
   reg [3 : 0]   csprng_ctrl_new;
   reg           csprng_ctrl_we;
 
-  reg [31 : 0]  read_data_new;
-  reg [31 : 0]  read_data_reg;
+  reg [31 : 0]  tmp_read_data;
 
 
   //----------------------------------------------------------------
@@ -194,7 +193,7 @@ module trng_csprng(
   //----------------------------------------------------------------
   // Concurrent connectivity for ports etc.
   //----------------------------------------------------------------
-  assign read_data      = read_data_reg;
+  assign read_data      = tmp_read_data;
   assign error          = tmp_error;
   assign seed_ack       = seed_ack_reg;
   assign more_seed      = more_seed_reg;
@@ -268,7 +267,6 @@ module trng_csprng(
           num_rounds_reg      <= DEFAULT_NUM_ROUNDS;
           num_blocks_low_reg  <= DEFAULT_NUM_BLOCKS[31 : 0];
           num_blocks_high_reg <= DEFAULT_NUM_BLOCKS[63 : 32];
-          read_data_reg       <= 32'h00000000;
           csprng_ctrl_reg     <= CTRL_IDLE;
         end
       else
@@ -277,9 +275,6 @@ module trng_csprng(
           seed_ack_reg  <= seed_ack_new;
           seed_reg      <= seed_new;
 
-          if (cs)
-            read_data_reg <= read_data_new;
-
           if (enable_we)
             enable_reg <= enable_new;
 
@@ -335,7 +330,7 @@ module trng_csprng(
 
       rnd_ack             = 0;
 
-      read_data_new       = 32'h00000000;
+      tmp_read_data       = 32'h00000000;
       tmp_error           = 0;
 
       if (cs)
@@ -382,35 +377,50 @@ module trng_csprng(
               // Read operations.
               case (address)
                 // Read operations.
+                ADDR_NAME0:
+                  begin
+                    tmp_read_data = CORE_NAME0;
+                  end
+
+                ADDR_NAME1:
+                  begin
+                    tmp_read_data = CORE_NAME1;
+                  end
+
+                ADDR_VERSION:
+                  begin
+                    tmp_read_data = CORE_VERSION;
+                  end
+
                 ADDR_CTRL:
                   begin
-                    read_data_new = {30'h00000000, seed_reg, enable_reg};
+                    tmp_read_data = {30'h00000000, seed_reg, enable_reg};
                   end
 
                 ADDR_STATUS:
                   begin
-                    read_data_new = {30'h00000000, ready_reg, rnd_syn};
+                    tmp_read_data = {30'h00000000, ready_reg, rnd_syn};
                   end
 
                 ADDR_RND_DATA:
                   begin
-                    read_data_new = rnd_data;
+                    tmp_read_data = rnd_data;
                     rnd_ack  = 1;
                   end
 
                 ADDR_NUM_ROUNDS:
                   begin
-                    read_data_new = {27'h0000000, num_rounds_reg};
+                    tmp_read_data = {27'h0000000, num_rounds_reg};
                   end
 
                 ADDR_NUM_BLOCKS_LOW:
                   begin
-                    read_data_new = num_blocks_low_reg;
+                    tmp_read_data = num_blocks_low_reg;
                   end
 
                 ADDR_NUM_BLOCKS_HIGH:
                   begin
-                    read_data_new = num_blocks_high_reg;
+                    tmp_read_data = num_blocks_high_reg;
                   end
 
                 default:
diff --git a/src/rtl/trng_mixer.v b/src/rtl/trng_mixer.v
index 24ccaaa..449dc5c 100644
--- a/src/rtl/trng_mixer.v
+++ b/src/rtl/trng_mixer.v
@@ -214,8 +214,7 @@ module trng_mixer(
   reg         restart_reg;
   reg         restart_new;
 
-  reg [31 : 0] read_data_new;
-  reg [31 : 0] read_data_reg;
+  reg [31 : 0] tmp_read_data;
 
 
   //----------------------------------------------------------------
@@ -248,7 +247,7 @@ module trng_mixer(
   //----------------------------------------------------------------
   // Concurrent connectivity for ports etc.
   //----------------------------------------------------------------
-  assign read_data      = read_data_reg;
+  assign read_data      = tmp_read_data;
   assign error          = tmp_error;
   assign security_error = 0;
 
@@ -349,16 +348,12 @@ module trng_mixer(
           entropy_timeout_reg      <= DEFAULT_ENTROPY_TIMEOUT;
           entropy_timeout_ctr_reg  <= 24'h000000;
           entropy_collect_ctrl_reg <= CTRL_IDLE;
-          read_data_reg            <= 32'h00000000;
           mixer_ctrl_reg           <= CTRL_IDLE;
         end
       else
         begin
           restart_reg <= restart_new;
 
-          if (cs)
-            read_data_reg <= read_data_new;
-
           if (block00_we)
             block00_reg <= muxed_entropy;
 
@@ -493,7 +488,7 @@ module trng_mixer(
       restart_new         = 0;
       entropy_timeout_new = 24'h000000;
       entropy_timeout_we  = 0;
-      read_data_new       = 32'h00000000;
+      tmp_read_data       = 32'h00000000;
       tmp_error           = 0;
 
       if (cs)
@@ -530,17 +525,17 @@ module trng_mixer(
                 // Read operations.
                 ADDR_MIXER_CTRL:
                   begin
-                    read_data_new = {30'h00000000, restart_reg, enable_reg};
+                    tmp_read_data = {30'h00000000, restart_reg, enable_reg};
                   end
 
                 ADDR_MIXER_STATUS:
                   begin
-                    read_data_new = 32'h00000000;
+                    tmp_read_data = 32'h00000000;
                   end
 
                 ADDR_MIXER_TIMEOUT:
                   begin
-                    read_data_new = {8'h00, entropy_timeout_reg};
+                    tmp_read_data = {8'h00, entropy_timeout_reg};
                   end
 
                 default: