From 8f7a8e5789d9feb7b8ec1ac9e2041c8dbbc1395c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 26 Sep 2014 14:39:15 +0200 Subject: Update of rosc entropy after synthesis of the trng. --- src/rtl/rosc_entropy.v | 8 +++++--- src/rtl/rosc_entropy_core.v | 4 ++-- 2 files changed, 7 insertions(+), 5 deletions(-) (limited to 'src/rtl') diff --git a/src/rtl/rosc_entropy.v b/src/rtl/rosc_entropy.v index 815c606..404ddae 100644 --- a/src/rtl/rosc_entropy.v +++ b/src/rtl/rosc_entropy.v @@ -47,15 +47,17 @@ module rosc_entropy( output wire [31 : 0] read_data, output wire error, + input wire discard, + input wire test_mode, + output wire security_error, + output wire entropy_enabled, output wire [31 : 0] entropy_data, output wire entropy_valid, input wire entropy_ack, output wire [7 : 0] debug, - input wire debug_update, - - output wire security_error + input wire debug_update ); diff --git a/src/rtl/rosc_entropy_core.v b/src/rtl/rosc_entropy_core.v index 98e08e6..6fb48ec 100644 --- a/src/rtl/rosc_entropy_core.v +++ b/src/rtl/rosc_entropy_core.v @@ -203,7 +203,7 @@ module rosc_entropy_core( //---------------------------------------------------------------- always @* begin : debug_out - debug_delay_ctr_new = 8'h00000000; + debug_delay_ctr_new = 32'h00000000; debug_delay_ctr_we = 0; debug_we = 0; @@ -215,7 +215,7 @@ module rosc_entropy_core( if (debug_delay_ctr_reg == DEBUG_DELAY) begin - debug_delay_ctr_new = 8'h00000000; + debug_delay_ctr_new = 32'h00000000; debug_delay_ctr_we = 1; debug_we = 1; end -- cgit v1.2.3