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-rw-r--r--src/rtl/README.md38
-rw-r--r--src/rtl/rosc_entropy.v2
-rw-r--r--src/rtl/rosc_entropy_core.v16
3 files changed, 9 insertions, 47 deletions
diff --git a/src/rtl/README.md b/src/rtl/README.md
deleted file mode 100644
index 4986410..0000000
--- a/src/rtl/README.md
+++ /dev/null
@@ -1,38 +0,0 @@
-rosc_entropy
-============
-
-Digital entropy source based on on jitter between multiple, digital ring
-oscillators. The entropy source is used in the TRNG as one of several
-entropy sources feeding the mixer.
-
-
-## Functionality ##
-
-The digital oscillators are created using adders. The carry out from the
-adder are inverted and fed back into the adder as carry in. In
-combination with operand values we basically get an inverted signal (the
-carry out) that toggles reapeatedly. By having the operands externally
-defined, synthesis tools in general will not optimize them away.
-
-The carry out signal is sampled with a clock that toggles at a much
-slower rate than the intrinsic toggle rate of the carry out signal. In a
-modern FPGA, the toggle rate may be 400+ MHz while the sample rate might
-be 10 kHz. This sample time allows the differences in intrinsic toggle
-frequency between separate oscillators to drift apart after sampling.
-
-The entropy source contains 32 separate oscillators. The outputs from
-the oscillators are XOR-combined to create a single entropy bit. Entropy
-bits are collected into 32-bit words which are provided to entropy
-consumers.
-
-
-## Implementation Results ##
-
-The entropy source has been implemented, tested and shown to produce
-good quality entropy (using the ent estimation tool etc) in Altera
-Cyclone-IV and Cyclone-V devices as well as in Xilinx Spartan-6.
-
-The Xilinx synthesis tool will try to optimize the combinational loop
-away. (More specifically, it claims that the oscillator sample registers
-will have a fixed value.). There is therefore an attribute in the source
-code to force the tool to preserve the register.
diff --git a/src/rtl/rosc_entropy.v b/src/rtl/rosc_entropy.v
index 485b516..179f41c 100644
--- a/src/rtl/rosc_entropy.v
+++ b/src/rtl/rosc_entropy.v
@@ -169,7 +169,7 @@ module rosc_entropy(
begin
if (!reset_n)
begin
- enable_reg <= 1;
+ enable_reg <= 1'h1;
op_a_reg <= DEFAULT_OP_A;
op_b_reg <= DEFAULT_OP_B;
end
diff --git a/src/rtl/rosc_entropy_core.v b/src/rtl/rosc_entropy_core.v
index 51ded81..cb5ca4b 100644
--- a/src/rtl/rosc_entropy_core.v
+++ b/src/rtl/rosc_entropy_core.v
@@ -162,15 +162,15 @@ module rosc_entropy_core(
begin
if (!reset_n)
begin
- ent_shift_reg <= 32'h00000000;
- entropy_reg <= 32'h00000000;
- entropy_valid_reg <= 0;
- bit_ctr_reg <= 8'h00;
- sample_ctr_reg <= 8'h00;
- debug_delay_ctr_reg <= 32'h00000000;
+ ent_shift_reg <= 32'h0;
+ entropy_reg <= 32'h0;
+ entropy_valid_reg <= 1'h0;
+ bit_ctr_reg <= 8'h0;
+ sample_ctr_reg <= 8'h0;
+ debug_delay_ctr_reg <= 32'h0;
warmup_cycle_ctr_reg <= WARMUP_CYCLES;
- debug_reg <= 8'h00;
- debug_update_reg <= 0;
+ debug_reg <= 8'h0;
+ debug_update_reg <= 1'h0;
end
else
begin