(1) Added warmup functionality to the rosc entropy provider. (2) Changed name of enable port in the core. (3) Added a rudimentary makefile to allos building and linting of the rosc entropy core.

2 files changed, 47 insertions, 12 deletions

diff --git a/src/rtl/rosc_entropy.v b/src/rtl/rosc_entropy.v
index 0a7e60b..77af1f5 100644
--- a/src/rtl/rosc_entropy.v
+++ b/src/rtl/rosc_entropy.v
@@ -141,7 +141,7 @@ module rosc_entropy(
                          .clk(clk),
                          .reset_n(reset_n),
 
-                         .en(enable_reg),
+                         .enable(enable_reg),
 
                          .opa(op_a_reg),
                          .opb(op_b_reg),
diff --git a/src/rtl/rosc_entropy_core.v b/src/rtl/rosc_entropy_core.v
index cd70f8a..4a43eb9 100644
--- a/src/rtl/rosc_entropy_core.v
+++ b/src/rtl/rosc_entropy_core.v
@@ -40,7 +40,7 @@ module rosc_entropy_core(
                          input wire           clk,
                          input wire           reset_n,
 
-                         input wire           en,
+                         input wire           enable,
 
                          input wire [31 : 0]  opa,
                          input wire [31 : 0]  opb,
@@ -60,6 +60,8 @@ module rosc_entropy_core(
   //----------------------------------------------------------------
   // Parameters.
   //----------------------------------------------------------------
+  // 100000 cycles warmup delay.
+  localparam WARMUP_CYCLES     = 24'h0186a0;
   localparam ADDER_WIDTH       = 1;
   localparam DEBUG_DELAY       = 32'h002c4b40;
   localparam NUM_SHIFT_BITS    = 8'h20;
@@ -69,6 +71,11 @@ module rosc_entropy_core(
   //----------------------------------------------------------------
   // Registers including update variables and write enable.
   //----------------------------------------------------------------
+  reg [23 : 0] warmup_cycle_ctr_reg;
+  reg [23 : 0] warmup_cycle_ctr_new;
+  reg          warmup_cycle_ctr_we;
+  reg          warmup_done;
+
   reg [31 : 0] ent_shift_reg;
   reg [31 : 0] ent_shift_new;
   reg          ent_shift_we;
@@ -117,7 +124,7 @@ module rosc_entropy_core(
   assign rosc_outputs  = rosc_dout;
   assign raw_entropy   = ent_shift_reg;
   assign entropy_data  = entropy_reg;
-  assign entropy_valid = entropy_valid_reg;
+  assign entropy_valid = entropy_valid_reg & warmup_done;
   assign debug         = debug_reg;
 
 
@@ -155,20 +162,24 @@ module rosc_entropy_core(
     begin
       if (!reset_n)
         begin
-          ent_shift_reg       <= 32'h00000000;
-          entropy_reg         <= 32'h00000000;
-          entropy_valid_reg   <= 0;
-          bit_ctr_reg         <= 8'h00;
-          sample_ctr_reg      <= 8'h00;
-          debug_delay_ctr_reg <= 32'h00000000;
-          debug_reg           <= 8'h00;
-          debug_update_reg    <= 0;
+          ent_shift_reg        <= 32'h00000000;
+          entropy_reg          <= 32'h00000000;
+          entropy_valid_reg    <= 0;
+          bit_ctr_reg          <= 8'h00;
+          sample_ctr_reg       <= 8'h00;
+          debug_delay_ctr_reg  <= 32'h00000000;
+          warmup_cycle_ctr_reg <= WARMUP_CYCLES;
+          debug_reg            <= 8'h00;
+          debug_update_reg     <= 0;
         end
       else
         begin
           sample_ctr_reg   <= sample_ctr_new;
           debug_update_reg <= debug_update;
 
+          if (warmup_cycle_ctr_we)
+            warmup_cycle_ctr_reg <= warmup_cycle_ctr_new;
+
           if (ent_shift_we)
             begin
               ent_shift_reg <= ent_shift_new;
@@ -229,6 +240,30 @@ module rosc_entropy_core(
 
 
   //----------------------------------------------------------------
+  // warmup_ctr
+  //
+  // Logic for the warmup counter. This counter starts
+  // decreasing when reset lifts and decreases until reaching zero.
+  // At zero the counter stops and asserts warmup_done.
+  //----------------------------------------------------------------
+  always @*
+    begin : warmup_ctr
+      if (warmup_cycle_ctr_reg == 0)
+        begin
+          warmup_cycle_ctr_new = 24'h000000;
+          warmup_cycle_ctr_we  = 0;
+          warmup_done          = 1;
+        end
+      else
+        begin
+          warmup_cycle_ctr_new = warmup_cycle_ctr_reg - 1'b1;
+          warmup_cycle_ctr_we  = 1;
+          warmup_done          = 0;
+        end
+    end
+
+
+  //----------------------------------------------------------------
   // entropy_out
   //
   // Logic that implements the random output control. If we have
@@ -289,7 +324,7 @@ module rosc_entropy_core(
 
       sample_ctr_new = sample_ctr_reg + 1'b1;
 
-      if (en && (sample_ctr_reg == SAMPLE_CLK_CYCLES))
+      if (enable && warmup_done && (sample_ctr_reg == SAMPLE_CLK_CYCLES))
         begin
           sample_ctr_new   = 8'h00;
           bit_ctr_inc      = 1;