Updates to fix bugs found during synthesis. Adding more debug outputs in API. Adding security error port for future internal health tests.

1 files changed, 6 insertions, 8 deletions

diff --git a/src/rtl/rosc.v b/src/rtl/rosc.v
index afcc9bf..5557353 100644
--- a/src/rtl/rosc.v
+++ b/src/rtl/rosc.v
@@ -55,13 +55,7 @@ module rosc #(parameter WIDTH = 2)
   // Registers.
   //----------------------------------------------------------------
   reg dout_reg;
-
-
-  //----------------------------------------------------------------
-  // Wires.
-  //----------------------------------------------------------------
-  reg [WIDTH : 0] sum;
-  reg 	          cin;
+  reg dout_new;
 
 
   //----------------------------------------------------------------
@@ -83,7 +77,7 @@ module rosc #(parameter WIDTH = 2)
            begin
              if (we)
                begin
-                 dout_reg <= cin;
+                 dout_reg <= dout_new;
                end
            end
        end
@@ -99,8 +93,12 @@ module rosc #(parameter WIDTH = 2)
   //----------------------------------------------------------------
   always @*
     begin: adder_osc
+      reg [WIDTH : 0] sum;
+      reg             cin;
+
       cin = ~sum[WIDTH];
       sum = opa + opb + cin;
+      dout_new = sum[WIDTH];
     end
 endmodule // rosc