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-rw-r--r--src/rtl/avalanche_entropy.v16
-rw-r--r--src/rtl/avalanche_entropy_core.v76
2 files changed, 60 insertions, 32 deletions
diff --git a/src/rtl/avalanche_entropy.v b/src/rtl/avalanche_entropy.v
index 3774f27..7ba76ac 100644
--- a/src/rtl/avalanche_entropy.v
+++ b/src/rtl/avalanche_entropy.v
@@ -85,7 +85,6 @@ module avalanche_entropy(
localparam ADDR_ENTROPY = 8'h20;
localparam ADDR_DELTA = 8'h30;
-
localparam CORE_NAME0 = 32'h6578746e; // "extn"
localparam CORE_NAME1 = 32'h6f697365; // "oise"
localparam CORE_VERSION = 32'h302e3130; // "0.10"
@@ -94,19 +93,18 @@ module avalanche_entropy(
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
- reg [31 : 0] tmp_read_data;
-
- reg enable_reg;
- reg enable_new;
- reg enable_we;
+ reg enable_reg;
+ reg enable_new;
+ reg enable_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
- wire [31 : 0] delta;
+ reg [31 : 0] tmp_read_data;
+ reg tmp_error;
- reg tmp_error;
+ wire [31 : 0] delta;
//----------------------------------------------------------------
@@ -147,7 +145,7 @@ module avalanche_entropy(
begin
if (!reset_n)
begin
- enable_reg <= 1;
+ enable_reg <= 1;
end
else
begin
diff --git a/src/rtl/avalanche_entropy_core.v b/src/rtl/avalanche_entropy_core.v
index 582b4b6..115a94d 100644
--- a/src/rtl/avalanche_entropy_core.v
+++ b/src/rtl/avalanche_entropy_core.v
@@ -72,13 +72,20 @@ module avalanche_entropy_core(
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
- parameter DEBUG_DELAY = 32'h002c4b40;
- parameter MIN_ENTROPY_BITS = 6'h20;
+ // 100000 cycles warmup delay.
+ localparam WARMUP_CYCLES = 24'h0186a0;
+ localparam DEBUG_DELAY = 32'h002c4b40;
+ localparam MIN_ENTROPY_BITS = 6'h20;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
+ reg [23 : 0] warmup_cycle_ctr_reg;
+ reg [23 : 0] warmup_cycle_ctr_new;
+ reg warmup_cycle_ctr_we;
+ reg warmup_done;
+
reg noise_sample0_reg;
reg noise_sample_reg;
@@ -118,19 +125,14 @@ module avalanche_entropy_core(
//----------------------------------------------------------------
- // Wires.
- //----------------------------------------------------------------
-
-
- //----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
- assign entropy_valid = entropy_valid_reg;
+ assign entropy_valid = entropy_valid_reg & warmup_done;
assign entropy_data = entropy_reg;
+ assign entropy_enabled = enable_reg & warmup_done;
assign delta = delta_reg;
assign debug = debug_reg;
- assign entropy_enabled = enable_reg;
//----------------------------------------------------------------
@@ -140,20 +142,21 @@ module avalanche_entropy_core(
begin
if (!reset_n)
begin
- noise_sample0_reg <= 1'b0;
- noise_sample_reg <= 1'b0;
- flank0_reg <= 1'b0;
- flank1_reg <= 1'b0;
- entropy_valid_reg <= 1'b0;
- entropy_reg <= 32'h00000000;
- entropy_bit_reg <= 1'b0;
- bit_ctr_reg <= 6'h00;
- cycle_ctr_reg <= 32'h00000000;
- delta_reg <= 32'h00000000;
- debug_delay_ctr_reg <= 32'h00000000;
- debug_reg <= 8'h00;
- debug_update_reg <= 0;
- enable_reg <= 0;
+ noise_sample0_reg <= 1'b0;
+ noise_sample_reg <= 1'b0;
+ flank0_reg <= 1'b0;
+ flank1_reg <= 1'b0;
+ entropy_valid_reg <= 1'b0;
+ entropy_reg <= 32'h00000000;
+ entropy_bit_reg <= 1'b0;
+ bit_ctr_reg <= 6'h00;
+ cycle_ctr_reg <= 32'h00000000;
+ delta_reg <= 32'h00000000;
+ debug_delay_ctr_reg <= 32'h00000000;
+ warmup_cycle_ctr_reg <= WARMUP_CYCLES;
+ debug_reg <= 8'h00;
+ debug_update_reg <= 0;
+ enable_reg <= 0;
end
else
begin
@@ -171,6 +174,9 @@ module avalanche_entropy_core(
enable_reg <= enable;
+ if (warmup_cycle_ctr_we)
+ warmup_cycle_ctr_reg <= warmup_cycle_ctr_new;
+
if (delta_we)
begin
delta_reg <= cycle_ctr_reg;
@@ -226,6 +232,30 @@ module avalanche_entropy_core(
//----------------------------------------------------------------
+ // warmup_ctr
+ //
+ // Logic for the warmup counter. This counter starts
+ // decreasing when reset lifts and decreases until reaching zero.
+ // At zero the counter stops and asserts warmup_done.
+ //----------------------------------------------------------------
+ always @*
+ begin : warmup_ctr
+ if (warmup_cycle_ctr_reg == 0)
+ begin
+ warmup_cycle_ctr_new = 24'h000000;
+ warmup_cycle_ctr_we = 0;
+ warmup_done = 1;
+ end
+ else
+ begin
+ warmup_cycle_ctr_new = warmup_cycle_ctr_reg - 1'b1;
+ warmup_cycle_ctr_we = 1;
+ warmup_done = 0;
+ end
+ end
+
+
+ //----------------------------------------------------------------
// entropy_collect
//
// We collect entropy by adding the current state of the