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-rw-r--r--src/rtl/avalanche_entropy.v2
-rw-r--r--src/rtl/avalanche_entropy_core.v28
2 files changed, 15 insertions, 15 deletions
diff --git a/src/rtl/avalanche_entropy.v b/src/rtl/avalanche_entropy.v
index fc70f5f..8eac786 100644
--- a/src/rtl/avalanche_entropy.v
+++ b/src/rtl/avalanche_entropy.v
@@ -145,7 +145,7 @@ module avalanche_entropy(
begin
if (!reset_n)
begin
- enable_reg <= 1;
+ enable_reg <= 1'h1;
end
else
begin
diff --git a/src/rtl/avalanche_entropy_core.v b/src/rtl/avalanche_entropy_core.v
index 6c7c70d..d39ced1 100644
--- a/src/rtl/avalanche_entropy_core.v
+++ b/src/rtl/avalanche_entropy_core.v
@@ -142,21 +142,21 @@ module avalanche_entropy_core(
begin
if (!reset_n)
begin
- noise_sample0_reg <= 1'b0;
- noise_sample_reg <= 1'b0;
- flank0_reg <= 1'b0;
- flank1_reg <= 1'b0;
- entropy_valid_reg <= 1'b0;
- entropy_reg <= 32'h00000000;
- entropy_bit_reg <= 1'b0;
- bit_ctr_reg <= 6'h00;
- cycle_ctr_reg <= 32'h00000000;
- delta_reg <= 32'h00000000;
- debug_delay_ctr_reg <= 32'h00000000;
+ noise_sample0_reg <= 1'h0;
+ noise_sample_reg <= 1'h0;
+ flank0_reg <= 1'h0;
+ flank1_reg <= 1'h0;
+ entropy_valid_reg <= 1'h0;
+ entropy_reg <= 32'h0;
+ entropy_bit_reg <= 1'h0;
+ bit_ctr_reg <= 6'h0;
+ cycle_ctr_reg <= 32'h0;
+ delta_reg <= 32'h0;
+ debug_delay_ctr_reg <= 32'h0;
warmup_cycle_ctr_reg <= WARMUP_CYCLES;
- debug_reg <= 8'h00;
- debug_update_reg <= 0;
- enable_reg <= 0;
+ debug_reg <= 8'h0;
+ debug_update_reg <= 1'h0;
+ enable_reg <= 1'h0;
end
else
begin