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authorPaul Selkirk <paul@psgd.org>2015-11-17 23:40:22 -0500
committerPaul Selkirk <paul@psgd.org>2015-11-17 23:40:22 -0500
commit5742813ab43fec9fa90d970f086f1e266875b8f3 (patch)
treee27ca8b9832983ff36968ce04cf44caadc863b14 /src/rtl
parent6bc2d51db70e599d010971aefc1d01c854622e40 (diff)
Harmonize status valid bit with other cores.
Diffstat (limited to 'src/rtl')
-rw-r--r--src/rtl/avalanche_entropy.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/rtl/avalanche_entropy.v b/src/rtl/avalanche_entropy.v
index 6ae824a..fc70f5f 100644
--- a/src/rtl/avalanche_entropy.v
+++ b/src/rtl/avalanche_entropy.v
@@ -80,7 +80,7 @@ module avalanche_entropy(
localparam CTRL_ENABLE_BIT = 0;
localparam ADDR_STATUS = 8'h09;
- localparam STATUS_VALID_BIT = 0;
+ localparam STATUS_VALID_BIT = 1;
localparam ADDR_ENTROPY = 8'h20;
localparam ADDR_DELTA = 8'h30;
@@ -203,13 +203,13 @@ module avalanche_entropy(
ADDR_CTRL:
begin
- tmp_read_data = {31'h00000000, enable_reg};
+ tmp_read_data[CTRL_ENABLE_BIT] = enable_reg;
end
ADDR_STATUS:
begin
- tmp_read_data = {31'h00000000, entropy_valid};
- end
+ tmp_read_data[STATUS_VALID_BIT] = entropy_valid;
+ end
ADDR_ENTROPY:
begin