platform/terasic_c5g
====================

Platform-specific files for the TerasIC C5G development board.

## Introduction ##
This includes the Verilog top-level files and build systems for Terasic
with a UART interface.

## Status ##
***(2015-03-16)***
Reorganized. Built using Altera Quarus 14.1.

***(2014-03-07)***
Initial version. Build using Altera Quarus 13.1.

- Cyclone 5 GX device
- 2847 ALMs and
- 3665 registers
- 86 MHz