From f06583ef515bae8f24d696e0df75a425bc47c2bb Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Thu, 28 Aug 2014 10:29:48 -0400 Subject: initial commit of Novena code for coretest --- src/rtl/coretest_hashes.v | 318 ++++++++++++++++++++++++++++++++++++++++++++++ src/rtl/novena_fpga.v | 147 +++++++++++++++++++++ 2 files changed, 465 insertions(+) create mode 100644 src/rtl/coretest_hashes.v create mode 100644 src/rtl/novena_fpga.v (limited to 'src/rtl') diff --git a/src/rtl/coretest_hashes.v b/src/rtl/coretest_hashes.v new file mode 100644 index 0000000..5076047 --- /dev/null +++ b/src/rtl/coretest_hashes.v @@ -0,0 +1,318 @@ +//====================================================================== +// +// coretest_hashes.v +// ----------------- +// Top level wrapper that creates the Cryptech coretest system. +// The wrapper contains instances of external interface, coretest +// and the core to be tested. And if more than one core is +// present the wrapper also includes address and data muxes. +// +// +// Author: Joachim Strombergson +// Copyright (c) 2014, SUNET +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module coretest_hashes( + input wire clk, + input wire reset_n, + + // External interface. + input wire SCL, + input wire SDA, + output wire SDA_pd, + + output wire [7 : 0] debug + ); + + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + parameter I2C_ADDR_PREFIX = 8'h00; + parameter SHA1_ADDR_PREFIX = 8'h10; + parameter SHA256_ADDR_PREFIX = 8'h20; + parameter SHA512_ADDR_PREFIX = 8'h30; + + + //---------------------------------------------------------------- + // Wires. + //---------------------------------------------------------------- + // Coretest connections. + wire coretest_reset_n; + wire coretest_cs; + wire coretest_we; + wire [15 : 0] coretest_address; + wire [31 : 0] coretest_write_data; + reg [31 : 0] coretest_read_data; + reg coretest_error; + + // i2c connections + wire i2c_rxd_syn; + wire [7 : 0] i2c_rxd_data; + wire i2c_rxd_ack; + wire i2c_txd_syn; + wire [7 : 0] i2c_txd_data; + wire i2c_txd_ack; + reg i2c_cs; + reg i2c_we; + reg [7 : 0] i2c_address; + reg [31 : 0] i2c_write_data; + wire [31 : 0] i2c_read_data; + wire i2c_error; + wire [7 : 0] i2c_debug; + + // sha1 connections. + reg sha1_cs; + reg sha1_we; + reg [7 : 0] sha1_address; + reg [31 : 0] sha1_write_data; + wire [31 : 0] sha1_read_data; + wire sha1_error; + wire [7 : 0] sha1_debug; + + // sha256 connections. + reg sha256_cs; + reg sha256_we; + reg [7 : 0] sha256_address; + reg [31 : 0] sha256_write_data; + wire [31 : 0] sha256_read_data; + wire sha256_error; + wire [7 : 0] sha256_debug; + + // sha512 connections. + reg sha512_cs; + reg sha512_we; + reg [7 : 0] sha512_address; + reg [31 : 0] sha512_write_data; + wire [31 : 0] sha512_read_data; + wire sha512_error; + wire [7 : 0] sha512_debug; + + + //---------------------------------------------------------------- + // Concurrent assignment. + //---------------------------------------------------------------- + assign debug = i2c_debug; + + + //---------------------------------------------------------------- + // Core instantiations. + //---------------------------------------------------------------- + coretest coretest( + .clk(clk), + .reset_n(reset_n), + + .rx_syn(i2c_rxd_syn), + .rx_data(i2c_rxd_data), + .rx_ack(i2c_rxd_ack), + + .tx_syn(i2c_txd_syn), + .tx_data(i2c_txd_data), + .tx_ack(i2c_txd_ack), + + // Interface to the core being tested. + .core_reset_n(coretest_reset_n), + .core_cs(coretest_cs), + .core_we(coretest_we), + .core_address(coretest_address), + .core_write_data(coretest_write_data), + .core_read_data(coretest_read_data), + .core_error(coretest_error) + ); + + + i2c i2c( + .clk(clk), + .reset_n(!reset_n), // active high + + .SCL(SCL), + .SDA(SDA), + .SDA_pd(SDA_pd), + .i2c_device_addr(8'h1E), + + .rxd_syn(i2c_rxd_syn), + .rxd_data(i2c_rxd_data), + .rxd_ack(i2c_rxd_ack), + + .txd_syn(i2c_txd_syn), + .txd_data(i2c_txd_data), + .txd_ack(i2c_txd_ack), + + .cs(i2c_cs), + .we(i2c_we), + .address(i2c_address), + .write_data(i2c_write_data), + .read_data(i2c_read_data), + .error(i2c_error), + + .debug(i2c_debug) + ); + + + sha1 sha1( + // Clock and reset. + .clk(clk), + .reset_n(reset_n), + + // Control. + .cs(sha1_cs), + .we(sha1_we), + + // Data ports. + .address(sha1_address), + .write_data(sha1_write_data), + .read_data(sha1_read_data), + .error(sha1_error) + ); + + + sha256 sha256( + // Clock and reset. + .clk(clk), + .reset_n(reset_n), + + // Control. + .cs(sha256_cs), + .we(sha256_we), + + // Data ports. + .address(sha256_address), + .write_data(sha256_write_data), + .read_data(sha256_read_data), + .error(sha256_error) + ); + + + sha512 sha512( + // Clock and reset. + .clk(clk), + .reset_n(reset_n), + + // Control. + .cs(sha512_cs), + .we(sha512_we), + + // Data ports. + .address(sha512_address), + .write_data(sha512_write_data), + .read_data(sha512_read_data), + .error(sha512_error) + ); + + + //---------------------------------------------------------------- + // address_mux + // + // Combinational data mux that handles addressing between + // cores using the 32-bit memory like interface. + //---------------------------------------------------------------- + always @* + begin : address_mux + // Default assignments. + coretest_read_data = 32'h00000000; + coretest_error = 0; + + i2c_cs = 0; + i2c_we = 0; + i2c_address = 8'h00; + i2c_write_data = 32'h00000000; + + sha1_cs = 0; + sha1_we = 0; + sha1_address = 8'h00; + sha1_write_data = 32'h00000000; + + sha256_cs = 0; + sha256_we = 0; + sha256_address = 8'h00; + sha256_write_data = 32'h00000000; + + sha512_cs = 0; + sha512_we = 0; + sha512_address = 8'h00; + sha512_write_data = 32'h00000000; + + + case (coretest_address[15 : 8]) + I2C_ADDR_PREFIX: + begin + i2c_cs = coretest_cs; + i2c_we = coretest_we; + i2c_address = coretest_address[7 : 0]; + i2c_write_data = coretest_write_data; + coretest_read_data = i2c_read_data; + coretest_error = i2c_error; + end + + + SHA1_ADDR_PREFIX: + begin + sha1_cs = coretest_cs; + sha1_we = coretest_we; + sha1_address = coretest_address[7 : 0]; + sha1_write_data = coretest_write_data; + coretest_read_data = sha1_read_data; + coretest_error = sha1_error; + end + + + SHA256_ADDR_PREFIX: + begin + sha256_cs = coretest_cs; + sha256_we = coretest_we; + sha256_address = coretest_address[7 : 0]; + sha256_write_data = coretest_write_data; + coretest_read_data = sha256_read_data; + coretest_error = sha256_error; + end + + + SHA512_ADDR_PREFIX: + begin + sha512_cs = coretest_cs; + sha512_we = coretest_we; + sha512_address = coretest_address[7 : 0]; + sha512_write_data = coretest_write_data; + coretest_read_data = sha512_read_data; + coretest_error = sha512_error; + end + + + default: + begin + end + endcase // case (coretest_address[15 : 8]) + end // address_mux + +endmodule // coretest_hashes + +//====================================================================== +// EOF coretest_hashes.v +//====================================================================== diff --git a/src/rtl/novena_fpga.v b/src/rtl/novena_fpga.v new file mode 100644 index 0000000..fd0f667 --- /dev/null +++ b/src/rtl/novena_fpga.v @@ -0,0 +1,147 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013, Andrew "bunnie" Huang +// +// See the NOTICE file distributed with this work for additional +// information regarding copyright ownership. The copyright holder +// licenses this file to you under the Apache License, Version 2.0 +// (the "License"); you may not use this file except in compliance +// with the License. You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, +// code distributed under the License is distributed on an +// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +// KIND, either express or implied. See the License for the +// specific language governing permissions and limitations +// under the License. +////////////////////////////////////////////////////////////////////////////// + +/// note: must set "-g UnusedPin:Pullnone" to avoid conflicts with unused pins + +`timescale 1ns / 1ps + +module novena_fpga( + // CPU side mapping + input wire [15:0] EIM_DA, + output reg EIM_A16, // relay of the trigger output + output reg EIM_A17, // relay of the trigger data (read path) + + // connector side mapping + //input wire F_LVDS_N3, // output of trigger + //input wire F_DX2, // output of trigger + //output wire F_LVDS_N5, // trigger reset + output wire F_LVDS_P4, // trigger reset + //inout wire F_LVDS_P5, // trigger data (bidir) + //input wire F_DX18, // trigger data in from sticker (DUT->CPU) + output wire F_LVDS_P11, // trigger data out to sticker (CPU->DUT) + //output wire F_LVDS_N8, // trigger clock + //output wire F_DX14, // trigger clock + + output wire F_LVDS_N7, // drive TPI data line + output wire F_LVDS_P7, // drive TPI signal lines + + output wire F_DX15, // 1 = drive 5V, 0 = drive 3V to DUT + + output wire F_LVDS_CK1_N, + output wire F_LVDS_CK1_P, + output wire F_LVDS_N11, + + output wire F_LVDS_N0, + output wire F_LVDS_P0, + output wire F_DX1, + + output wire F_LVDS_N15, + output wire F_LVDS_P15, + output wire F_LVDS_NC, + + //input wire F_DX11, + //input wire F_DX3, + //input wire F_DX0, + + //input wire F_LVDS_CK0_P, + //input wire F_LVDS_CK0_N, + //input wire F_LVDS_P9, + + //input wire [1:0] EIM_CS, + //input wire EIM_LBA, + + input wire CLK2_N, + input wire CLK2_P, + output wire FPGA_LED2, + + input wire I2C3_SCL, + inout wire I2C3_SDA, + + input wire RESETBMCU, + output wire F_DX17, // dummy + output wire APOPTOSIS +); + wire clk; + + IBUFGDS clkibufgds( + .I(CLK2_P), + .IB(CLK2_N), + .O(clk) + ); + + assign FPGA_LED2 = 1'b1; + + assign APOPTOSIS = 1'b0; + assign F_DX15 = 1'b1; //+5V P_DUT + + // OE on bank to drive signals; signal not inverted in software + assign F_LVDS_P7 = !EIM_DA[3]; + // OE on bank to drive the data; signal not inverted in software + assign F_LVDS_N7 = !EIM_DA[4]; + assign F_LVDS_P4 = 1'b0; + assign F_LVDS_P11 = 1'b0; + assign F_LVDS_CK1_N = 1'b0; + assign F_LVDS_CK1_P = 1'b0; + assign F_LVDS_N11 = 1'b0; + assign F_LVDS_N0 = 1'b0; + assign F_LVDS_P0 = 1'b0; + assign F_DX1 = 1'b0; + assign F_LVDS_N15 = 1'b0; + assign F_LVDS_P15 = 1'b0; + assign F_LVDS_NC = 1'b0; + + // reduction and of EIM_DA, dummy-map to keep compiler quiet + assign F_DX17 = &EIM_DA | RESETBMCU; + + //////////////////////////////////// + ///// I2C register set + //////////////////////////////////// + wire SDA_pd; + wire SDA_int; + reg clk25; + + initial begin + clk25 <= 1'b0; + end + always @ (posedge clk) begin + clk25 <= ~clk25; + EIM_A16 <= 1'b0; + EIM_A17 <= 1'b0; + end + + IOBUF #( + .DRIVE(8), + .SLEW("SLOW") + ) IOBUF_sda ( + .IO(I2C3_SDA), + .I(1'b0), + .T(!SDA_pd), + .O(SDA_int) + ); + + coretest_hashes top( + .clk(clk25), + .reset_n(1'b1), + + .SCL(I2C3_SCL), + .SDA(SDA_int), + .SDA_pd(SDA_pd) + ); + +endmodule -- cgit v1.2.3