From 38d62bec91558562f738dd4730d7a9dbb3fabf7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Wed, 1 Apr 2015 16:28:03 +0200 Subject: Refactor: Moved all address defines for cryptech cores into a common header file. --- eim/sw/trng_tester_eim.c | 94 +++--------------------------------------------- 1 file changed, 4 insertions(+), 90 deletions(-) (limited to 'eim/sw/trng_tester_eim.c') diff --git a/eim/sw/trng_tester_eim.c b/eim/sw/trng_tester_eim.c index eb30045..f60aeec 100644 --- a/eim/sw/trng_tester_eim.c +++ b/eim/sw/trng_tester_eim.c @@ -1,4 +1,4 @@ -/* +/* * trng_tester.c * -------------- * This program sends several commands to the TRNG subsystem @@ -6,10 +6,10 @@ * * Note: This version of the program talks to the FPGA over an EIM bus. * - * + * * Author: Paul Selkirk * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: @@ -48,6 +48,7 @@ #include #include "tc_eim.h" +#include "cryptech_memory_map.h" #define WAIT_STATS /* report number of status reads before core says "ready" */ @@ -56,93 +57,6 @@ int quiet = 0; int repeat = 0; int num_words = 10; -/* memory segments for core families */ -#define SEGMENT_OFFSET_GLOBALS EIM_BASE_ADDR + 0x000000 -#define SEGMENT_OFFSET_HASHES EIM_BASE_ADDR + 0x010000 -#define SEGMENT_OFFSET_RNGS EIM_BASE_ADDR + 0x020000 -#define SEGMENT_OFFSET_CIPHERS EIM_BASE_ADDR + 0x030000 - -#define CORE_SIZE (0x100 << 2) - -/* addresses and codes common to all cores */ -#define ADDR_NAME0 (0x0 << 2) -#define ADDR_NAME1 (0x1 << 2) -#define ADDR_VERSION (0x2 << 2) - -/* At segment 0, we have board-level register and communication channel registers */ -#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x00 * CORE_SIZE) -#define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0 -#define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1 -#define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION -#define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + (0xFF << 2) - -#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x01 * CORE_SIZE) -#define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0 -#define COMM_ADDR_NAME1 COMM_ADDR_BASE + ADDR_NAME1 -#define COMM_ADDR_VERSION COMM_ADDR_BASE + ADDR_VERSION - -/* addresses and codes for the TRNG cores */ -#define TRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x00 * CORE_SIZE) -#define TRNG_ADDR_NAME0 TRNG_ADDR_BASE + ADDR_NAME0 -#define TRNG_ADDR_NAME1 TRNG_ADDR_BASE + ADDR_NAME1 -#define TRNG_ADDR_VERSION TRNG_ADDR_BASE + ADDR_VERSION -#define TRNG_ADDR_CTRL TRNG_ADDR_BASE + (0x10 << 2) -#define TRNG_CTRL_DISCARD 1 -#define TRNG_CTRL_TEST_MODE 2 -#define TRNG_ADDR_STATUS TRNG_ADDR_BASE + (0x11 << 2) -/* no status bits defined */ -#define TRNG_ADDR_DELAY TRNG_ADDR_BASE + (0x13 << 2) - -#define ENTROPY1_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x05 * CORE_SIZE) -#define ENTROPY1_ADDR_NAME0 ENTROPY1_ADDR_BASE + ADDR_NAME0 -#define ENTROPY1_ADDR_NAME1 ENTROPY1_ADDR_BASE + ADDR_NAME1 -#define ENTROPY1_ADDR_VERSION ENTROPY1_ADDR_BASE + ADDR_VERSION -#define ENTROPY1_ADDR_CTRL ENTROPY1_ADDR_BASE + (0x10 << 2) -#define ENTROPY1_CTRL_ENABLE 1 -#define ENTROPY1_ADDR_STATUS ENTROPY1_ADDR_BASE + (0x11 << 2) -#define ENTROPY1_STATUS_VALID 1 -#define ENTROPY1_ADDR_ENTROPY ENTROPY1_ADDR_BASE + (0x20 << 2) -#define ENTROPY1_ADDR_DELTA ENTROPY1_ADDR_BASE + (0x30 << 2) - -#define ENTROPY2_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x06 * CORE_SIZE) -#define ENTROPY2_ADDR_NAME0 ENTROPY2_ADDR_BASE + ADDR_NAME0 -#define ENTROPY2_ADDR_NAME1 ENTROPY2_ADDR_BASE + ADDR_NAME1 -#define ENTROPY2_ADDR_VERSION ENTROPY2_ADDR_BASE + ADDR_VERSION -#define ENTROPY2_ADDR_CTRL ENTROPY2_ADDR_BASE + (0x10 << 2) -#define ENTROPY2_CTRL_ENABLE 1 -#define ENTROPY2_ADDR_STATUS ENTROPY2_ADDR_BASE + (0x11 << 2) -#define ENTROPY2_STATUS_VALID 1 -#define ENTROPY2_ADDR_OPA ENTROPY2_ADDR_BASE + (0x18 << 2) -#define ENTROPY2_ADDR_OPB ENTROPY2_ADDR_BASE + (0x19 << 2) -#define ENTROPY2_ADDR_ENTROPY ENTROPY2_ADDR_BASE + (0x20 << 2) -#define ENTROPY2_ADDR_RAW ENTROPY2_ADDR_BASE + (0x21 << 2) -#define ENTROPY2_ADDR_ROSC ENTROPY2_ADDR_BASE + (0x22 << 2) - -#define MIXER_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0a * CORE_SIZE) -#define MIXER_ADDR_NAME0 MIXER_ADDR_BASE + ADDR_NAME0 -#define MIXER_ADDR_NAME1 MIXER_ADDR_BASE + ADDR_NAME1 -#define MIXER_ADDR_VERSION MIXER_ADDR_BASE + ADDR_VERSION -#define MIXER_ADDR_CTRL MIXER_ADDR_BASE + (0x10 << 2) -#define MIXER_CTRL_ENABLE 1 -#define MIXER_CTRL_RESTART 2 -#define MIXER_ADDR_STATUS MIXER_ADDR_BASE + (0x11 << 2) -/* no status bits defined */ -#define MIXER_ADDR_TIMEOUT MIXER_ADDR_BASE + (0x20 << 2) - -#define CSPRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0b * CORE_SIZE) -#define CSPRNG_ADDR_NAME0 CSPRNG_ADDR_BASE + ADDR_NAME0 -#define CSPRNG_ADDR_NAME1 CSPRNG_ADDR_BASE + ADDR_NAME1 -#define CSPRNG_ADDR_VERSION CSPRNG_ADDR_BASE + ADDR_VERSION -#define CSPRNG_ADDR_CTRL CSPRNG_ADDR_BASE + (0x10 << 2) -#define CSPRNG_CTRL_ENABLE 1 -#define CSPRNG_CTRL_SEED 2 -#define CSPRNG_ADDR_STATUS CSPRNG_ADDR_BASE + (0x11 << 2) -#define CSPRNG_STATUS_VALID 1 -#define CSPRNG_ADDR_RANDOM CSPRNG_ADDR_BASE + (0x20 << 2) -#define CSPRNG_ADDR_NROUNDS CSPRNG_ADDR_BASE + (0x40 << 2) -#define CSPRNG_ADDR_NBLOCKS_LO CSPRNG_ADDR_BASE + (0x41 << 2) -#define CSPRNG_ADDR_NBLOCKS_HI CSPRNG_ADDR_BASE + (0x42 << 2) - /* ---------------- sanity test case ---------------- */ int TC0() -- cgit v1.2.3