From 6a7b3fe6d5e83fc2ee236aae0799f74c92278685 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Wed, 29 Apr 2015 13:19:15 -0400 Subject: Cleanup: add error port. --- eim/rtl/novena_eim.v | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) (limited to 'eim/rtl/novena_eim.v') diff --git a/eim/rtl/novena_eim.v b/eim/rtl/novena_eim.v index 71b64a9..0d8c8d0 100644 --- a/eim/rtl/novena_eim.v +++ b/eim/rtl/novena_eim.v @@ -41,30 +41,30 @@ module novena_top ( // Differential input for 50 MHz general clock. - input wire gclk_p_pin, - input wire gclk_n_pin, + input wire gclk_p_pin, + input wire gclk_n_pin, // Reset controlled by the CPU. // this must be configured as input w/pullup - input wire reset_mcu_b_pin, + input wire reset_mcu_b_pin, // Cryptech avalanche noise board input and LED outputs - input wire ct_noise, + input wire ct_noise, output wire [7 : 0] ct_led, // EIM interface - input wire eim_bclk, // EIM burst clock. Started by the CPU. - input wire eim_cs0_n, // Chip select (active low). - inout wire [15 : 0] eim_da, // Bidirectional address and data port. - input wire [18: 16] eim_a, // MSB part of address port. - input wire eim_lba_n, // Latch address signal (active low). - input wire eim_wr_n, // write enable signal (active low). - input wire eim_oe_n, // output enable signal (active low). - output wire eim_wait_n, // Data wait signal (active low). + input wire eim_bclk, // EIM burst clock. Started by the CPU. + input wire eim_cs0_n, // Chip select (active low). + inout wire [15 : 0] eim_da, // Bidirectional address and data port. + input wire [18: 16] eim_a, // MSB part of address port. + input wire eim_lba_n, // Latch address signal (active low). + input wire eim_wr_n, // write enable signal (active low). + input wire eim_oe_n, // output enable signal (active low). + output wire eim_wait_n, // Data wait signal (active low). // Novena utility ports - output wire apoptosis_pin, // Hold low to not restart after config. - output wire led_pin // LED on edge close to the FPGA. + output wire apoptosis_pin, // Hold low to not restart after config. + output wire led_pin // LED on edge close to the FPGA. ); @@ -156,15 +156,13 @@ module novena_top .sys_clk(sys_clk), .sys_rst(sys_rst), - .noise(ct_noise), - .sys_eim_addr(sys_eim_addr), .sys_eim_wr(sys_eim_wr), .sys_eim_rd(sys_eim_rd), - .sys_write_data(sys_eim_dout), .sys_read_data(tmp_read_data), + .noise(ct_noise), .debug(ct_led) ); -- cgit v1.2.3