From 283bfbeeb7fb5767815c10ea98bb155638d4bfb3 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 17 Mar 2015 13:49:30 +0100 Subject: Rearrange cores. --- eim/build/.gitignore | 52 +++++++++++++++ eim/build/Makefile | 40 ++++++++++++ eim/build/xilinx.mk | 174 +++++++++++++++++++++++++++++++++++++++++++++++++++ eim/build/xilinx.opt | 42 +++++++++++++ 4 files changed, 308 insertions(+) create mode 100644 eim/build/.gitignore create mode 100644 eim/build/Makefile create mode 100644 eim/build/xilinx.mk create mode 100644 eim/build/xilinx.opt (limited to 'eim/build') diff --git a/eim/build/.gitignore b/eim/build/.gitignore new file mode 100644 index 0000000..01d7e9c --- /dev/null +++ b/eim/build/.gitignore @@ -0,0 +1,52 @@ +*.xrpt +_xmsgs +default.xreport +netlist.lst +*.bgn +*.bit +*.bld +*.cfi +*.drc +*.lso +*.lso +*.map +*.mcs +*.mrp +*.ncd +*.ngc +*.ngd +*.ngm +*.pcf +*.post_map.twr +*.post_map.twx +*.prj +*.prm +*.psr +*.scr +*.srp +*.twr +*.twx +*_bd.bmm +*_bitgen.xwb +*_bitgen.xwbt +*_err.twr +*_err.twx +*_par.grf +*_par.ncd +*_par.pad +*_par.par +*_par.ptwx +*_par.unroutes +*_par.xpi +*_par_pad.csv +*_par_pad.txt +*_summary.xml +*_usage.xml +par_usage_statistics.html +smartguide.ncd +smartpreview.twr +smartpreview.twr +usage_statistics_webtalk.html +webtalk.log +xlnx_auto* +xst diff --git a/eim/build/Makefile b/eim/build/Makefile new file mode 100644 index 0000000..c89d4ec --- /dev/null +++ b/eim/build/Makefile @@ -0,0 +1,40 @@ +project = novena_eim +vendor = xilinx +family = spartan6 +part = xc6slx45csg324-3 +top_module = novena_top +isedir = /opt/Xilinx/14.7/ISE_DS +xil_env = . $(isedir)/settings64.sh +ucf = ../ucf/novena_eim.ucf + +vfiles = \ + ../rtl/novena_eim.v \ + ../rtl/novena_regs.v \ + ../../common/rtl/novena_clkmgr.v \ + ../../common/rtl/ipcore/clkmgr_dcm.v \ + ../../../common/core_selector/src/rtl/core_selector.v \ + ../../../common/core_selector/src/rtl/global_selector.v \ + ../../../common/core_selector/src/rtl/cipher_selector.v \ + ../../../common/core_selector/src/rtl/hash_selector.v \ + ../../../common/core_selector/src/rtl/rng_selector.v \ + ../../../../comm/eim/src/rtl/cdc_bus_pulse.v \ + ../../../../comm/eim/src/rtl/eim_arbiter_cdc.v \ + ../../../../comm/eim/src/rtl/eim_arbiter.v \ + ../../../../comm/eim/src/rtl/eim_da_phy.v \ + ../../../../comm/eim/src/rtl/eim_indicator.v \ + ../../../../comm/eim/src/rtl/eim_regs.v \ + ../../../../comm/eim/src/rtl/eim.v \ + ../../../../hash/sha1/src/rtl/sha1.v \ + ../../../../hash/sha1/src/rtl/sha1_core.v \ + ../../../../hash/sha1/src/rtl/sha1_w_mem.v \ + ../../../../hash/sha256/src/rtl/sha256.v \ + ../../../../hash/sha256/src/rtl/sha256_core.v \ + ../../../../hash/sha256/src/rtl/sha256_k_constants.v \ + ../../../../hash/sha256/src/rtl/sha256_w_mem.v \ + ../../../../hash/sha512/src/rtl/sha512.v \ + ../../../../hash/sha512/src/rtl/sha512_core.v \ + ../../../../hash/sha512/src/rtl/sha512_h_constants.v \ + ../../../../hash/sha512/src/rtl/sha512_k_constants.v \ + ../../../../hash/sha512/src/rtl/sha512_w_mem.v + +include xilinx.mk diff --git a/eim/build/xilinx.mk b/eim/build/xilinx.mk new file mode 100644 index 0000000..f35cc98 --- /dev/null +++ b/eim/build/xilinx.mk @@ -0,0 +1,174 @@ +# The top level module should define the variables below then include +# this file. The files listed should be in the same directory as the +# Makefile. +# +# variable description +# ---------- ------------- +# project project name (top level module should match this name) +# top_module top level module of the project +# libdir path to library directory +# libs library modules used +# vfiles all local .v files +# xilinx_cores all local .xco files +# vendor vendor of FPGA (xilinx, altera, etc.) +# family FPGA device family (spartan3e) +# part FPGA part name (xc4vfx12-10-sf363) +# flashsize size of flash for mcs file (16384) +# optfile (optional) xst extra opttions file to put in .scr +# map_opts (optional) options to give to map +# par_opts (optional) options to give to par +# intstyle (optional) intstyle option to all tools +# ucf constraint file, defaults to $(project).ucf +# +# Library modules should have a modules.mk in their root directory, +# namely $(libdir)//module.mk, that simply adds to the vfiles +# and xilinx_cores variable. +# +# all the .xco files listed in xilinx_cores will be generated with core, with +# the resulting .v and .ngc files placed back in the same directory as +# the .xco file. +# +# TODO: .xco files are device dependant, should use a template based system + +coregen_work_dir ?= ./coregen-tmp +map_opts ?= -timing -ol high -detail -pr b -register_duplication -w +par_opts ?= -ol high +isedir ?= /opt/Xilinx/13.3/ISE_DS +xil_env ?= . $(isedir)/settings32.sh +flashsize ?= 8192 +ucf ?= $(project).ucf + +libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs)) +mkfiles = $(libmks) xilinx.mk +include $(libmks) + +corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc)) +local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc))) +vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v)) +junk += $(local_corengcs) + +.PHONY: default xilinx_cores clean twr etwr +default: $(project).bit $(project).mcs +xilinx_cores: $(corengcs) +twr: $(project).twr +etwr: $(project)_err.twr + +define cp_template +$(2): $(1) + cp $(1) $(2) +endef +$(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc))))) + +%.ngc %.v: %.xco + @echo "=== rebuilding $@" + if [ -d $(coregen_work_dir) ]; then \ + rm -rf $(coregen_work_dir)/*; \ + else \ + mkdir -p $(coregen_work_dir); \ + fi + cd $(coregen_work_dir); \ + $(xil_env); \ + coregen -b $$OLDPWD/$<; \ + cd - + xcodir=`dirname $<`; \ + basename=`basename $< .xco`; \ + if [ ! -r $(coregen_work_dir/$$basename.ngc) ]; then \ + echo "'$@' wasn't created."; \ + exit 1; \ + else \ + cp $(coregen_work_dir)/$$basename.v $(coregen_work_dir)/$$basename.ngc $$xcodir; \ + fi +junk += $(coregen_work_dir) + +date = $(shell date +%F-%H-%M) + +# some common junk +junk += *.xrpt + +programming_files: $(project).bit $(project).mcs + mkdir -p $@/$(date) + mkdir -p $@/latest + for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done + $(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - $(project).scr > $@/$(date)/$(project).scr + +$(project).mcs: $(project).bit + $(xil_env); \ + promgen -w -s $(flashsize) -p mcs -o $@ -u 0 $^ +junk += $(project).mcs $(project).cfi $(project).prm + +$(project).bit: $(project)_par.ncd + $(xil_env); \ + bitgen $(intstyle) -g UnusedPin:Pullnone -g DriveDone:yes -g StartupClk:Cclk -w $(project)_par.ncd $(project).bit +junk += $(project).bgn $(project).bit $(project).drc $(project)_bd.bmm + + +$(project)_par.ncd: $(project).ncd + $(xil_env); \ + if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd; then \ + :; \ + else \ + $(MAKE) etwr; \ + fi +junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad +junk += $(project)_par_pad.csv $(project)_par_pad.txt +junk += $(project)_par.grf $(project)_par.ptwx +junk += $(project)_par.unroutes $(project)_par.xpi + +$(project).ncd: $(project).ngd + if [ -r $(project)_par.ncd ]; then \ + cp $(project)_par.ncd smartguide.ncd; \ + smartguide="-smartguide smartguide.ncd"; \ + else \ + smartguide=""; \ + fi; \ + $(xil_env); \ + map $(intstyle) $(map_opts) $$smartguide $< +junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map +junk += smartguide.ncd $(project).psr +junk += $(project)_summary.xml $(project)_usage.xml + +$(project).ngd: $(project).ngc $(ucf) + $(xil_env); ngdbuild $(intstyle) $(project).ngc -uc $(ucf) +junk += $(project).ngd $(project).bld + +$(project).ngc: $(vfiles) $(local_corengcs) $(project).scr $(project).prj + $(xil_env); xst $(intstyle) -ifn $(project).scr +junk += xlnx_auto* $(top_module).lso $(project).srp +junk += netlist.lst xst $(project).ngc + +$(project).prj: $(vfiles) $(mkfiles) + for src in $(vfiles); do echo "verilog work $$src" >> $(project).tmpprj; done + sort -u $(project).tmpprj > $(project).prj + rm -f $(project).tmpprj +junk += $(project).prj + +optfile += $(wildcard $(project).opt) +top_module ?= $(project) +$(project).scr: $(optfile) $(mkfiles) ./xilinx.opt + echo "run" > $@ + echo "-p $(part)" >> $@ + echo "-top $(top_module)" >> $@ + echo "-ifn $(project).prj" >> $@ + echo "-ofn $(project).ngc" >> $@ + cat ./xilinx.opt $(optfile) >> $@ +junk += $(project).scr + +$(project).post_map.twr: $(project).ncd + $(xil_env); trce -e 10 $< $(project).pcf -o $@ +junk += $(project).post_map.twr $(project).post_map.twx smartpreview.twr + +$(project).twr: $(project)_par.ncd + $(xil_env); trce $< $(project).pcf -o $(project).twr +junk += $(project).twr $(project).twx smartpreview.twr + +$(project)_err.twr: $(project)_par.ncd + $(xil_env); trce -e 10 $< $(project).pcf -o $(project)_err.twr +junk += $(project)_err.twr $(project)_err.twx +junk += $(project).lso $(project)_bitgen.xwb $(project)_bitgen.xwbt +junk += usage_statistics_webtalk.html par_usage_statistics.html webtalk.log _xmsgs default.xreport + +.gitignore: $(mkfiles) + echo programming_files $(junk) | sed 's, ,\n,g' > .gitignore + +clean:: + rm -rf $(junk) diff --git a/eim/build/xilinx.opt b/eim/build/xilinx.opt new file mode 100644 index 0000000..7fe9d8b --- /dev/null +++ b/eim/build/xilinx.opt @@ -0,0 +1,42 @@ +-ifmt mixed +-ofmt NGC +-opt_mode speed +-opt_level 1 +-iuc NO +-keep_hierarchy no +-netlist_hierarchy as_optimized +-rtlview no +-glob_opt AllClockNets +-read_cores yes +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +#-dsp_utilization_ratio 100 +-safe_implementation No +-fsm_extract YES +-fsm_encoding Auto +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-rom_style Auto +-shreg_extract YES +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +#-use_dsp48 auto +-iobuf YES +-max_fanout 500 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 -- cgit v1.2.3