From c44c8a77b56778c951fb09f94a577057573dbfa7 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Fri, 17 Jul 2015 10:31:26 -0400 Subject: experimental modexps6 (which requires changing the read timing on all other cores) --- eim/build/xilinx.mk | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'eim/build/xilinx.mk') diff --git a/eim/build/xilinx.mk b/eim/build/xilinx.mk index 8065e45..8a81ef9 100644 --- a/eim/build/xilinx.mk +++ b/eim/build/xilinx.mk @@ -31,7 +31,9 @@ # TODO: .xco files are device dependant, should use a template based system coregen_work_dir ?= ./coregen-tmp -map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -xe n +#map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -xe n +# from https://github.com/fpga-logi/logi-hard/blob/master/build_lib/synth/xilinx.mk: +map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off par_opts ?= -ol high isedir ?= /opt/Xilinx/13.3/ISE_DS xil_env ?= . $(isedir)/settings32.sh -- cgit v1.2.3